Ports

Table 1. Integer Square Root Core Ports
Port Direction Description
reset_n Input Asynchronous system reset
1: Core is active
0: Reset
sysclk Input System clock input
din [Data Width-1:0] Input Input integer number
calcen Input 1: Start calculation
0: Stop calculation
clken Input 1: Enable clock to latch registers
0: Disable clock to latch
vout [(Data Width/2)-1:0] Output Square root result
rout [Data Width/2:0] Output Remainder
calcend Output 1: Calculation completed
0: Calculation in progress or no calculation
sqrtidle Output 1: Core is idle
0: Core is busy