Integer Square Root Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example design targets the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board by implementing a Integer Square Root module in the FPGA.

Table 1. Titanium Example Design Implementation
FPGA	Mode	Logic and Adders	Flip-flops	Memory Blocks	DSP48 Blocks	f_MAX (MHz)^¹	Efinity® Version^²
Ti60 F225 C4	Continuous	610	512	0	0	339	2021.2
Ti60 F225 C4	Single	139	126	0	0	239	2021.2

Table 2. Trion® Example Design Implementation
FPGA	Mode	Logic Utilizations (LUTs)	Registers	Memory Blocks	Multipliers	f_MAX (MHz)^¹	Efinity® Version^²
T20 BGA256 C4	Continuous	560	730	0	0	156	2021.1
T20 BGA256 C4	Single	192	126	0	0	112	2021.1

¹ Using default parameter settings.

² Using Verilog HDL.