This demo (watchdogTimer directory) shows how to utilize watchdog timer.

The watchdog timer has two counters, counter 0 and counter 1. Both counters runsimultaneously and each counter has its own limit. When the software resets the watchdog timer, both counters reset too. If the watchdog timer does not reset,

When counter 0 has reached its limit, the watchdog timer sends an interrupt to the PLIC, which is triggered as an external interrupt in the software. During the interrupt routine, you can try to recover the software or prepare for a proper shutdown or reset.

When counter 1 has reached its limit, watchdog timer asserts the top level pin, system_watchdog_hardPanic. User can use the signal from this pin to implement their reset or recovery logic for the system.

For more detail of the driver, refer to WatchDog Timer Driver.

Newlib

By default, newlib-nano is used for this demo.

See also: User Debug Configuration - To learn more about User Debug Configuration.

Execution Sequence:

The following shows the expected execution sequence:

***Starting WatchDog Timer Demo***
Watchdog timer timeout = 3s .. 
Pat the watchdog every 2500ms for 3 times then wait for soft panic trigger .. 
Watchdog patting will stop after 3 soft panic trigger.. 
 
Pat the watchdog .. 
Pat the watchdog .. 
Pat the watchdog .. 
Assume software gone wrong here .. 
Assume software gone wrong here .. 
Assume software gone wrong here .. 
Pat the watchdog .. 
Soft panic count=1 
Assume software gone wrong here .. 
 
Pat the watchdog .. 
Soft panic count=2 
Pat the watchdog .. 
Pat the watchdog .. 
Pat the watchdog .. 
Assume software gone wrong here .. 
Assume software gone wrong here .. 
Assume software gone wrong here .. 
Pat the watchdog .. 
Soft panic count=3 
Assume software gone wrong here .. 
 
Soft panic count=4 
stop pat the watchdog this time and watchdog will reset system after 3s ..

It will mentioned that the system has been reset in console:

Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Info : New GDB Connection: 1, Target fpga_spinal.cpu0, state: halted
Warn : Target Descriptions Supported, but disabled
Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x006a0a79 (mfg: 0x53c (Efinix Inc), part: 0x06a0, ver: 0x0)
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x006a0a79 (mfg: 0x53c (Efinix Inc), part: 0x06a0, ver: 0x0)
Info : Disabling abstract command writes to CSRs.
Info : [fpga_spinal.cpu0] Hart unexpectedly reset!
Info : [fpga_spinal.cpu1] Hart unexpectedly reset!
Info : [fpga_spinal.cpu2] Hart unexpectedly reset!
Info : [fpga_spinal.cpu3] Hart unexpectedly reset!