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Sapphire SoC DS
Sapphire SoC UG
Sapphire HP SoC DS
Sapphire HP SoC UG
RISC-V Embedded IDE UG
Board Support Package
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vexriscv.h
Go to the documentation of this file.
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// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
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// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
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#pragma once
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#ifndef VEX_RISCV_H_
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#define VEX_RISCV_H_
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#include "
riscv.h
"
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#include "
type.h
"
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#if __riscv_xlen == 32
// Currently Only implemented in Vex-i RV32
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//Invalidate the whole data cache
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#define data_cache_invalidate_all() asm(".word(0x500F)");
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//Invalidate all the data cache ways lines which could store the given address
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#define data_cache_invalidate_address(address) \
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({ \
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asm volatile( \
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".word ((0x500F) | (regnum_%0 << 15));" \
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: \
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: "r" (address) \
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); \
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})
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#endif
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//Invalidate the whole instruction cache
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#define instruction_cache_invalidate() asm("fence.i");
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#endif
// VEX_RISCV_H_
riscv.h
RISC-V related functions and definitions.
type.h
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