Sapphire SoC DS Sapphire SoC UG Sapphire HP SoC DS Sapphire HP SoC UG RISC-V Embedded IDE UG Board Support Package
Loading...
Searching...
No Matches
vexriscv.h
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6#pragma once
7#ifndef VEX_RISCV_H_
8#define VEX_RISCV_H_
9
10#include "riscv.h"
11#include "type.h"
12
13#if __riscv_xlen == 32 // Currently Only implemented in Vex-i RV32
14//Invalidate the whole data cache
15#define data_cache_invalidate_all() asm(".word(0x500F)");
16
17//Invalidate all the data cache ways lines which could store the given address
18#define data_cache_invalidate_address(address) \
19({ \
20 asm volatile( \
21 ".word ((0x500F) | (regnum_%0 << 15));" \
22 : \
23 : "r" (address) \
24 ); \
25})
26#endif
27
28//Invalidate the whole instruction cache
29#define instruction_cache_invalidate() asm("fence.i");
30
31
32#endif // VEX_RISCV_H_
RISC-V related functions and definitions.