Sapphire RISC-V SoC: IRQ Control

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Overview

RISC-V CSR Interrupt Management (MIE/MSTATUS).

Note: This module controls the processor's willingness to accept interrupts. It does not configure the external PLIC, but rather the CPU's internal gates for Software, Timer, and External (PLIC) interrupts.

To enable IRQ for external interrupt:

Please refer to uartInterruptDemo.
irq_setTrapVector(trap_entry);

irq_setType(IRQ_EXTERNAL);

irq_enable();

trap_entry
void trap_entry(void)
The Main Trap Entry Point (Naked).
Definition mtrap.c:72

irq_enable
void irq_enable(void)
Enable Global Interrupts (MIE bit).
Definition irq.c:56

irq_setType
void irq_setType(cpu_irq_t enable)
Enable specific CPU interrupt sources.
Definition irq.c:76

irq_setTrapVector
void irq_setTrapVector(void(*trap_vector)(void))
Set the Machine Trap Vector (mtvec).
Definition irq.c:46

IRQ_EXTERNAL
@ IRQ_EXTERNAL
Definition irq.h:98

To enable IRQ for Timer interrupt:

Please refer to userTimerDemo.
irq_setTrapVector(trap_entry);

irq_setType(IRQ_TIMER);

irq_enable();

IRQ_TIMER
@ IRQ_TIMER
Definition irq.h:97

To enable IRQ for Software interrupt:

Please refer to clintTimerInterrupDemo.
irq_setTrapVector(trap_entry);

irq_setType(IRQ_SOFTWARE);

irq_enable();

IRQ_SOFTWARE
@ IRQ_SOFTWARE
Definition irq.h:96

See also: irq.c

Topics
	API Functions
	Function definitions for IRQ driver.
	Data Structures
	Structs and Enums used by the driver.
	Default ISR Stubs
	Weak aliases for all PLIC interrupt sources.