RISC-V CSR Interrupt Management (MIE/MSTATUS).
Usage & Initialization.
- Note
- This module controls the processor's willingness to accept interrupts. It does not configure the external PLIC, but rather the CPU's internal gates for Software, Timer, and External (PLIC) interrupts.
To enable IRQ for external interrupt:
- Please refer to UART Interrupt Demo.
void trap_entry(void)
The Main Trap Entry Point (Naked).
void irq_enable(void)
Enable Global Interrupts (MIE bit).
void irq_setType(cpu_irq_t enable)
Enable specific CPU interrupt sources.
void irq_setTrapVector(void(*trap_vector)(void))
Set the Machine Trap Vector (mtvec).
To enable IRQ for Timer interrupt:
To enable IRQ for Software interrupt:
To register a custom IRQ Handler:
- Use irq_registerExt to register a custom handler for a specific PLIC interrupt source.
int custom_IRQ_handler()
{
return 1;
}
return 0;
}
void main() {
}
uart_instance_t uart0
Primary UART instance for standard I/O mapping.
void irq_registerExt(u32 gateway, irq_handler_t handler)
Override the default external IRQ handler for a specific gateway.
u32 uart_readStatus(uart_instance_t *inst)
Write 32-bit UART data.
void uart_write(uart_instance_t *inst, char data)
Writes a single character to the UART data register.
void uart_writeStatus(uart_instance_t *inst, u32 data)
Writes a value to the UART status register.
u32 uart_read(uart_instance_t *inst)
Read 32-bit UART data.
void uart_setRxInterruptEnable(uart_instance_t *inst, char Ena)
Enable or Disable UART RX Not Empty Interrupt.