Routing DDR Signals

• Minimize the PCB layer propagation variance.
• Avoid T-junctions for high-speed signals.
• Meet all delay matching requirements for PCB trace delays, different layer propagation velocity variances, and crosstalk.
• Surround the DRAM BGA pads with ground.
• To minimize the return path:
  • For the byte lanes, match all DQ and DQS traces by refering to Table 1.
  • Route data groups next to a VSS plane.
• Avoid placing high-speed DQ, DQS, address, and control signal across split planes. See Split Planes and Reference Planes for details.
• Use a gradual trace angle to reduce parasitic effects (avoid 90° trace angles). See Bending Traces for details.