PCB Layout Design Recommendation

Table 1. PCB Layout Design Recommendation (From FPGA to DRAM Pin)These numbers are the lengths calculated based on FR-4 material with Stripline (1 ps = ~5 mil). Please refer to Table 1 for actual delay requirement.
PCB Trace Recommendation Clock Signal Command/ Address Signals Control Signals Data Signals Unit
Signal CK A CKE CS DM DQ DQS
Impedance (±10%) 80 40 40 40 40 40 80 Ω
Blind via (Max)1 2 2 2 2 2 2 2 Qty
Width (Min) 5 5 5 5 5 5 5 mil
Spacing Between Trace
Serpentine spacing to itself (Min) 15 (3x width) mil
Spacing to DDR net (Min) 15 (3x width) mil
Spacing to non-DDR net (Min) 25 (5x width) mil
Spacing for byte_group to byte_group (Min) - - - - 25 (5x width)
Keep the same byte group in same PCB layer.
 mil
Spacing between differential pair 5 – 8 - - - - - 5 – 8 mil
Length Matching Tolerance
Length difference between differential pair (Max) 5 - - - - - 10 mil
Length difference within same group (Max) 5 62.5 62.5 62.5 375 375 10 mil
Signal length minus CK length - ±30 ±30 ±30 - - <0 mil
Signal length minus DQS length >0 - - - 0 – 375 0 – 375 - mil
Total Signal length for each signal (Max) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 inch
Sequence to route 5 4 7 6 3 2 1 -
Important: Include the FPGA package net length when calculating length matching tolerance. See Length Matching.
1 Refer to Length Matching for the Blind via requirement.