Efinix, Inc.
  • Ti90 Introduction
  • Ti90 Features
    • Ti90 Package-Dependent Resources
    • Ti90 Available Package Options
  • Ti90 Device Core Functional Description
    • Ti90 XLR Cell
    • Ti90 Embedded Memory
      • Ti90 True Dual-Port Mode
      • Ti90 Simple Dual-Port Mode
    • Ti90 DSP Block
    • Ti90 Clock and Control Network
      • Ti90 Clock Sources that Drive the Global and Regional Networks
      • Ti90 Driving the Global Network
      • Ti90 Driving the Regional Network
      • Ti90 Driving the Local Network
  • Ti90 Device Interface Functional Description
    • Ti90 Interface Block Connectivity
    • Ti90 GPIO
      • Ti90 Features for HVIO and HSIO Configured as GPIO
        • Ti90 Double-Data I/O
        • Ti90 Programmable Delay Chains
      • Ti90 HVIO
      • Ti90 HSIO
        • Ti90 HSIO Configured as GPIO
        • Ti90 HSIO Configured as LVDS
        • Ti90 HSIO Configured as MIPI Lane
      • Ti90 I/O Banks
    • Ti90 DDR DRAM Interface
    • Ti90 MIPI D-PHY
      • Ti90 MIPI RX D-PHY
      • Ti90 MIPI TX D-PHY
    • Ti90 Oscillator
    • Ti90 PLL
      • Ti90 Dynamic Phase Shift
    • Ti90 Spread-Spectrum Clocking PLL
    • Ti90 Single-Event Upset Detection
    • Ti90 Internal Reconfiguration Block
  • Ti90 Security Feature
  • Ti90 Power Sequence
    • Ti90 Power-Up Sequence
    • Ti90 Power-Down Sequence
    • Ti90 Power Supply Current Transient
    • Ti90 Unused Resources and Features
  • Ti90 Configuration
    • Ti90 Supported Configuration Modes
  • Ti90 Characteristics and Timing
    • Ti90 DC and Switching Characteristics
    • Ti90 HSIO Electrical and Timing Specifications
    • Ti90 MIPI Electrical Specifications and Timing
      • Ti90 MIPI Reset Timing
    • Ti90 PLL Timing and AC Characteristics
    • Ti90 Configuration Timing
      • Ti90 JTAG Mode
      • Ti90 SPI Active Mode
      • Ti90 SPI Passive Mode
  • Ti90 Pinout Description
    • Ti90 Configuration Pins
    • Ti90 Dedicated DDR Pinout
    • Ti90 Dedicated MIPI D-PHY Pinout
    • Ti90 Pin States
  • Ti90 Interface Floorplan
  • Ti90 Efinity Software Support
  • Ti90 Ordering Codes
  • Ti90 Revision History

Ti90 Internal Reconfiguration Block

The Ti90 FPGAs have built-in hardware that supports an internal reconfiguration feature. The Ti90 can reconfigure itself from a bitstream image stored in flash memory.

Note: Refer to AN 010: Using the Internal Reconfiguration Feature to Update Efinix FPGAs Remotely for details regarding reconfiguration.
Parent topic: Ti90 Device Interface Functional Description

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