Ti90 HSIO Electrical and Timing Specifications

The HSIO pins comply with the LVDS EIA/TIA-644 electrical specifications.

HSIO as LVDS, Sub-LVDS, Bus-LVDS, RSDS, Mini LVDS, and SLVS

Table 1. HSIO Electrical Specifications when Configured as LVDS
Parameter Description Test Conditions Min Typ Max Unit
LVDS TX
VCCIO LVDS transmitter voltage supply – 1.71 1.8 1.89 V
VOD Output differential voltage RL = 100 Ω 200 350 450 mV
Δ VOD Change in VOD – – – 50 mV
VOCM Output common mode voltage – 1.125 1.2 1.375 V
Δ VOCM Change in VOCM – – – 50 mV
LVDS RX
VID Input differential voltage – 100 – 600 mV
VICM Input common mode voltage (fmax <= 1000 Mbps) – 100 – 1,600 mV
Input common mode voltage (fmax > 1000 Mbps) – 700 – 1,400 mV
Vi Input voltage valid range – 0 – 1.89 V
Table 2. HSIO Timing Specifications when Configured as LVDS
Parameter Description Min Typ Max Unit
tLVDS_CPA LVDS TX reference clock output phase accuracy -5 – +5 %
tLVDS_skew LVDS TX lane-to-lane skew – 200 – ps
Table 3. HSIO Electrical Specifications when Configured as Sub-LVDS
Parameter Description Test Conditions Min Typ Max Unit
Sub-LVDS TX
VCCIO Sub-LVDS transmitter voltage supply – 1.71 1.8 1.89 V
VOD Output differential voltage RL = 100 Ω 100 150 200 mV
ΔVOD Change in VOD – – – 50 mV
VOCM Output common mode voltage – 0.8 0.9 1.0 V
ΔVOCM Change in VOCM – – – 50 mV
Sub-LVDS RX
VID Input differential voltage – 100 – 600 mV
VICM Input common mode voltage – 100 – 1600 mV
Vi Input voltage valid range – 0 – 1.89 V
Table 4. HSIO Electrical Specifications when Configured as Bus-LVDS
Parameter Description Test Conditions Min Typ Max Unit
Bus-LVDS TX
VCCIO Voltage supply for LVDS transmitter – 1.71 1.8 1.89 V
VOD Differential output voltage RL = 27 Ω 200 250 300 mV
ΔVOD Static difference of VOD (between 0 and 1) – – – 50 mV
VOC Output common mode voltage – 1.125 1.2 1.375 V
ΔVOC Output common mode voltage offset – – – 50 mV
Bus-LVDS RX
VID Differential input voltage – 100 – 600 mV
VIC Differential input common mode – 100 – 1600 mV
Vi Valid input voltage range – 0 – 1.89 V
Table 5. HSIO Electrical Specifications when Configured as RSDS, Mini LVDS and SLVS
IO standard VID (mV) VICM (mV) VOD (mV) VOCM (mV)
Min Max Min Max Min Typ Max Min Typ Max
RSDS 100 - 300 1400 100 200 600 500 1200 1400
Mini LVDS 200 600 400 1325 250 - 600 1000 1200 1400
SLVS 100 400 100 300 150 200 250 140 200 270

HSIO as High–Speed and Low-Power MIPI Lane

The MIPI transmitter and receiver lanes are compliant to the MIPI Alliance Specification for D-PHY Revision 1.1.

Table 6. HSIO DC Specifications when Configured as High–Speed MIPI TX Lane
Parameter Description Min Typ Max Unit
VCCIO High–speed transmitter voltage supply. 1.14 1.2 1.26 V
VCMTX High–speed transmit static common–mode voltage. 150 200 250 mV
|ΔVCMTX| VCMTX mismatch when output is Differential–1 or Differential–0. – – 5 mV
|VOD| High–speed transmit differential voltage. 140 200 270 mV
|ΔVOD| VOD mismatch when output is Differential–1 or Differential–0. – – 14 mV
VOHHS High–speed output high voltage. – – 360 mV
VCMRX Common mode voltage for high-speed receive mode. 70 – 330 mV
Table 7. HSIO DC Specifications when Configured as Low–Power MIPI TX Lane
Parameter Description Min Typ Max Unit
VOH Thevenin output high level. 1.1 1.2 1.3 V
VOL Thevenin output low level. -50 – 50 mV
ZOLP Output impedance of low-power transmitter. 110 – – Ω
Table 8. HSIO DC Specifications when Configured as High–Speed MIPI RX Lane
Parameter Description Min Typ Max Unit
VCMRX(DC) Common mode voltage high–speed receiver mode . 70 – 330 mV
VIDTH Differential input high threshold. – – 70 mV
VIDTL Differential input low threshold. -70 – – mV
VIHHS Single-ended input high voltage. – 460 mV
VILHS Single-ended input low voltage. -40 – – mV
Table 9. HSIO DC Specifications when Configured as Low–Power MIPI RX Lane
Parameter Description Min Typ Max Unit
VIH Logic 1 input voltage. 880 – – mV
VIL Logic 0 input voltage, not in ULP state. – – 550 mV
VIL-ULPS Logic 0 input voltage, ULPS state. – – 300 mV
VHYST Input hysteresis. 25 – – mV