Ti85 Transceiver Interface

The Ti85 high-speed transceiver interface is a multi-protocol, full duplex transceiver that supports data rates from 1.188 Gbps to 16 Gbps. It supports the PCIe 4.0, SGMII, and 10GBase-KR protocols, as well as a PMA Direct mode. You can use it in ×1, ×2, or ×4 configuration.

Note: All quads support SGMII, 10GBase-KR, and PMA Direct. All even quads support PCIe. All lanes must have the same link rate.
Table 1. Supported Protocols
Standard Number of Lanes Specification
PCIe Gen 1 ×1, ×2, ×4 PCI Express® Base Specification Revision 1.1
PCIe Gen 2 ×1, ×2, ×4 PCI Express® Base Specification Revision 2.1
PCIe Gen 3 ×1, ×2, ×4 PCI Express® Base Specification Revision 3.0
PCIe Gen 4 ×1, ×2, ×4 PCI Express® Base Specification Revision 4.0
SGMII ×1 IEEE std 802.3 clause 36
10GBase-KR ×1 IEEE std 802.3ap-2007
PMA Direct1 ×1, ×2, ×4 –
Note: The transceiver data rates vary by speed grade. Refer to Table 1 for the date rates.
Figure 1. Transceiver Used as PCIe
Figure 2. Transceiver Used as SGMII, 10GBase-KR, or PMA Direct
1 The maximum allowed channel insertion loss is 5 dB for data rates above 10.3125 Gbps, and 15 dB for data rates of 10.3125 Gbps or lower.