Efinix, Inc.
  • Ti85 Introduction
  • Ti85 Features
    • Ti85 Available Package Options
  • Ti85 Device Core Functional Description
    • Ti85 XLR Cell
    • Ti85 Embedded Memory
      • Ti85 True Dual-Port Mode
      • Ti85 Simple Dual-Port Mode
    • Ti85 DSP Block
    • Ti85 Clock and Control Network
      • Ti85 Clock Sources that Drive the Global and Regional Networks
      • Ti85 Driving the Global Network
      • Ti85 Driving the Regional Network
      • Ti85 Driving the Local Network
  • Ti85 Device Interface Functional Description
    • Ti85 Interface Block Connectivity
    • Ti85 GPIO
      • Ti85 Features for HVIO and HSIO Configured as GPIO
        • Ti85 Double-Data I/O
        • Ti85 Programmable Delay Chains
      • Ti85 HVIO
      • Ti85 HSIO
        • Ti85 HSIO Configured as GPIO
        • Ti85 HSIO Configured as LVDS
        • Ti85 HSIO Configured as MIPI Lane
      • Ti85 I/O Banks
    • Ti85 DDR DRAM Interface
    • Ti85 MIPI D-PHY
      • Ti85 MIPI RX D-PHY
      • Ti85 MIPI TX D-PHY
    • Ti85 Oscillator
    • Ti85 Fractional PLL
      • Ti85 Reference Clock Resource Assignments
      • Ti85 Programmable Duty Cycle
      • Ti85 Fractional Output Divider
      • Ti85 Spread-Spectrum Clocking
      • Ti85 Dynamic PLL Reconfiguration
      • Ti85 Dynamic Phase Shift
    • Ti85 Spread-Spectrum Clocking PLL
    • Ti85 Hardened RISC-V Block Interface
    • Ti85 Transceiver Interface
    • Ti85 Single-Event Upset Detection
    • Ti85 Internal Reconfiguration Block
  • Ti85 Security Feature
  • Ti85 Power Sequence
    • Ti85 Power-Up Sequence
    • Ti85 Power-Down Sequence
    • Ti85 Power Supply Current Transient
    • Ti85 Unused Resources and Features
  • Ti85 Configuration
    • Ti85 Supported Configuration Modes
  • Ti85 Characteristics and Timing
    • Ti85 DC and Switching Characteristics
    • Ti85 HSIO Electrical and Timing Specifications
    • Ti85 MIPI Electrical Specifications and Timing
      • Ti85 MIPI Reset Timing
    • Ti85 PLL Timing and AC Characteristics
    • Ti85 Configuration Timing
      • Ti85 JTAG Mode
      • Ti85 SPI Active Mode
      • Ti85 SPI Passive Mode
    • Ti85 Transceiver Specifications
  • Ti85 Pinout Description
    • Ti85 Configuration Pins
    • Ti85 Dedicated DDR Pinout
    • Ti85 Dedicated MIPI D-PHY Pinout
    • Ti85 Dedicated Transceiver Pinout
    • Ti85 Pin States
  • Ti85 Interface Floorplan
  • Ti85 Efinity Software Support
  • Ti85 Ordering Codes
  • Ti85 Revision History

Ti85 Characteristics and Timing

The following table shows the specification status for Ti85 packages.

Table 1. Package Status
Package Status
N441 Preliminary
N484 Preliminary
N576 Preliminary
N676 Preliminary
  • Ti85 DC and Switching Characteristics
  • Ti85 HSIO Electrical and Timing Specifications
  • Ti85 MIPI Electrical Specifications and Timing
  • Ti85 PLL Timing and AC Characteristics
  • Ti85 Configuration Timing
  • Ti85 Transceiver Specifications

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