Ti85 Power-Up Sequence

Figure 1. Power-Up Sequence
Important: You can only use one configuration channel at a time. Using SPI passive and JTAG at the same time can result in configuration failure.
  1. The CRESET_N input must stay low until all power supplies are powered up. Additionally, VQPS must always stay low unless you are blowing the Ti85 security fuses.
    Note: Refer to Fuse Programming Requirements if you need to blow the security fuses for the Ti85 FPGA on your board.
  2. Power up supplies in group 1 first. You can power up these supplies in any sequence.
    Important: Ensure the power ramp rate is within the values shown in Table 3.
  3. Power up the group 2 supplies in any sequence at a minimum delay of 10 µs after group 1 supplies have reached 90% of their nominal voltage levels.
  4. If you are using transceivers, the external reference clock must be ready before CRESET_N is released.
  5. Release the CRESET_N input to high at a minimum delay of 10 µs after all FPGA supplies have reached 90% of their nominal voltage levels.
  6. FPGA configuration can begin after there has been:
    • A 4.5 ms minimum delay after all supplies have reached at least 90% of their nominal voltage.
    • A tDMIN minimum delay after CRESET_N goes high (see Ti85 SPI Passive Mode and Ti85 JTAG Mode for the delay specification).
    Note: With the configuration bitstream stored in the SPI flash device and the SPI active hardware connection properly established, the SPI active configuration automatically starts after the CRESET_N signal transitions from low to high.
Table 1. Power-Up GroupsIf you are blowing the security fuses, refer to Fuse Programming Requirements.
Power-Up Sequence
Group 1 Group 2
VCC
VCCA
VDD_SOC
VCCAUX
VCCIO
VCCIO33
MIPI D-PHY
–
VCC18A_MIPI_TX
VCC18A_MIPI_RX
DDR DRAM controller
VDD_PHY
VDDPLL_MCB_TOP_PHY
VDDQ_PHY
VDDQX_PHY
VDDQ_CK_PHY
Transceivers1
VCC_SERDES, VDDA_C_Q, VDDA_D_Q, VDDA_H_Q
Note: Some DDR DRAM devices have a specific power-up sequence requirement. Ensure this requirement is met when the FPGA and memory share a power supply.
1 The transceiver supplies can be powered up in any sequence.