Features

  • High-density, low-power compute fabric
  • Built on process
  • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
  • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting
  • Versatile on-chip clocking
    • Low-skew global network supporting clock or control signals
    • Regional and local clock networks
    • Up to PLLs with support for fractional-N division, programmable duty cycle, spread-spectrum clocking, and dynamic reconfiguration
  • interface blocks
    • 32-bit quad-core hardened RISC-V block
    • Two high-speed transceiver banks, each with 4 lanes:
      • Supports data rates from 1.188 Gbps up to 16 Gbps per channel
      • PCIe Gen4 x4:
        • Compliant with the PCIe® 4.0, 3.0, 2.1, and 1.1 specifications
        • Support x1, x2, and x4 configurations
        • Configure as Root Port (RP) or End Point (EP)
        • Single Root IO Virtualization (SRIOV)
      • Supports SGMII and 10GBase-KR protocols, as well as PMA Direct
    • One PHY interfaces (supporting DQ widths) with memory controller hard IP
    • Two MIPI D-PHY RX and TX interfaces with speeds up to 2.5 Gbps
    • Two varieties of general-purpose I/O (GPIO) pins:
      • High-voltage I/O (HVIO) pins support 1.8, 2.5, and 3.3 V
      • Configurable high-speed I/O (HSIO) pins support
        • Single-ended and differential I/O
        • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps
        • MIPI lane (DSI and CSI) in high-speed and low-power modes, up to 1.5 Gbps
    • oscillator
    • Spread-Spectrum Clocking (SSC) PLL
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Supports internal reconfiguration
  • Single-event upset (SEU) detection feature
  • Optional security feature
    • Asymmetric bitstream authentication using RSA-4096
    • Bitstream encryption/decryption using AES-GCM
  • Fully supported by the software, an RTL-to-bitstream compiler
Important: All specifications are preliminary and pending hardware characterization.
Table 1. Resources
Logic Elements (LEs) eXchangeable Logic and Routing (XLR) Cells Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks ( Kbits) Embedded DSP Blocks
Total SRL81
Up to
Table 2. Package-Dependent Resources
Resource
Single-ended GPIO (maximum) HVIO
LVCMOS: 1.8, 2.5, 3.0, 3.3 V
LVTTL: 3.0, 3.3 V
 20 21 34 50 84
HSIO
LVCMOS, HSTL: 1.2, 1.5, 1.8 V
SSTL: 1.2, 1.35, 1.5, 1.8 V
 88 85 100 118 139
Differential GPIO (maximum) HSIO (LVDS, Differential HSTL, and SSTL) 44 42 50 59 69
HSIO (MIPI D-PHY Data Lanes) 29 34 36 46 58
HSIO (MIPI D-PHY Clock Lanes) 7 7 7 9 11
LPDDR4/4x PHY with memory controller 1 x16 1 x32 1 x32 1 x162 1 x32
LPDDR4x SDRAM 2 Gbits, up to 3,000 Mbps data rate, 16-bit data bus – – – 1 –
MIPI D-PHY Hard Blocks RX 1 1 2 2 2
TX or SSC PLL 1 1 2 2 2
Global clock or control signals from GPIO pins 22 24 27 30 30
Fractional PLLs 9 8 9 9 9
Transceiver banks3 PCIe 1xGen4 1xGen4 1xGen4 1xGen4 1xGen4
SGMII, 10GBase-KR, or PMA Direct up to 2 up to 2 up to 2 up to 2 up to 2
Note: The x32 LPDDR4/4x PHY with memory controller can be configured as x16 or x32 widths.
1 Number of XLR cells that can be configured as shift register with 8 maximum taps.
2 The PHY is connected to the LPDDR4/4x device in the package; it cannot be used to connect to an external memory device.
3 Refer to Ti85 Transceiver Specifications for the data rates supported by different speed grade devices.