Ti165 Introduction

The Titanium™ Ti165 FPGA features the high-density, low-power Efinix® Quantum® compute fabric wrapped with an I/O interface. This FPGA has a variety of features, such as a hardened RISC-V block, transceivers, LPDDR4 DRAM controller, and MIPI D-PHY.

The quad-core hardened RISC-V block has a 32-bit CPU featuring the ISA RISCV32I with M, A, C, F, and D extensions, and six pipeline stages. You utilize the hardened RISC-V block by instantiating the Sapphire High-Performance SoC, combining the speed and efficiency of a hardened RISC-V block with the flexibility of peripherals in soft logic.

The full-duplex transceivers support multiple protocols including PCIe® Gen4, SGMII, and 10GBase-KR, as well as a PMA Direct mode with data rates from 1.188 Gbps to 12.5 Gbps.

Ti165 FPGAs include a hardened MIPI D-PHY, which you can use with Efinix® MIPI CSI-2 and DSI controller IP cores to create multi-camera, high definition vision systems, edge computing, and hardware acceleration systems. Additionally, these FPGAs have a hardened DDR DRAM controller block that supports LPDDR4 DRAM interfaces.

Together, these features enable a wide variety of applications such as PCIe cards, RF repeaters and radio units, small cell/massive MIMO, cable modems, machine vision, automotive, AV equipment and broadcast, medical imaging, and video bridges.