Ti165 Transceiver Specifications

The following tables describe the transceiver specifications.

Table 1. Transceiver Data Rate

Standard	Speed Grade	Data Rate per Lane			Unit
		Min.	Typ.	Max.
PCIe Gen1	All	–	2.5	–	Gbps
PCIe Gen2	All	–	5	–	Gbps
PCIe Gen3	All	–	8	–	Gbps
PCIe Gen4	C4, I4, C3, I3	–	16	–	Gbps
10GBase-KR	All	–	10.3125	–	Gbps
SGMII	All	–	1.25	–	Gbps
PMA Direct	C4, I4, C3, I3, C4L, I4L	1.188	–	12.5	Gbps
	C3L, I3L	1.188	–	10.31251	Gbps

Note: For PMA Direct RX insertion loss guidelines, refer to the "PMA Direct" topic in AN 063: High-Speed Transceiver Design Guidelines.

Table 2. Transceiver Common PLL Specification

Description	Condition	Min.	Typ.	Max.	Unit
Input clock frequency	PCIe - SRIS disabled	99.97	100	100.03	MHz
	10GBase-KR	156.22	156.25	156.28	MHz
	SGMII	156.22	156.25	156.28	MHz
		–	100	–	MHz
		–	62.5	–	MHz
	PMA Direct	19.19	–	156.28	MHz
VCO frequency	–	4.375	–	5.16	GHz

Table 3. Transceiver Lane PLL Specification

Description	Condition	Min.	Typ.	Max.	Unit
Input clock frequency	–	500	–	1000	MHz
VCO frequency	–	8	–	16	GHz

Table 4. Transceiver External Refclk Specification

Symbol, Description	Condition	Min.	Typ.	Max.	Unit
VI, Input voltage valid range	–	0	–	VDDA	V
VID, Differential peak-to-peak input voltage	–	0.4	0.8	VDDA x 2	V
SSC frequency deviation	–		–	5000	ppm
Ramp rate	–	0.6	–		V/ns
Duty cycle	–	45	–	55	%
Spread-spectrum modulating clock frequency	–	30	–	33	kHz
Phase Noise	Offset = 100 Hz	–	–	-80	dBc/Hz
	Offset = 1 kHz	–	–	-100	dBc/Hz
	Offset = 10 kHz	–	–	-120	dBc/Hz
	Offset = 100 kHz	–	–	-130	dBc/Hz
	Offset = 1 MHz	–	–	-140	dBc/Hz
RTERM, Internal termination resistor2	–	40	50	62.5	Ω

Note: The I/O standard for the transceiver external reference clock complies with the PCIe HCSL reference clock standard.

Table 5. Transmitter Specification

Description	Condition	Min.	Typ.	Max.	Unit
VOD, Differential output voltage	–	0.8	–	1.2	V
Lane-to-lane skew	Within the same quad	–	–	1741	ps
RJ, Random jitter	–	–	–	0.15	UI
DJ, Deterministic jitter	–	–	–	0.15	UI
DCDJ, Duty Cycle Distortion jitter	–	–	–	0.035	UI
TJ, Total jitter	–	–	–	0.28	UI

Table 6. Receiver Specification

Description	Min.	Typ.	Max.	Unit
VID, Differential peak-to-peak input voltage (externally AC-coupled)	–	–	1.6	V
ZDIFF-DC, DC differential input impedance	80	100	120	Ω
RJ, Random jitter	–	–	0.224	UI
DJ, Deterministic jitter	–	–	0.376	UI
SJ, Sinosoidal jitter	–	–	0.1	UI
TJ, Total jitter	–	–	0.7	UI
Reference clock to RX data PPM difference	-300	–	+300	ppm

Table 7. APB Clock

Description	Condition	Min.	Typ.	Max.	Unit
APB clock frequency	–	–	–	200	MHz