Efinix, Inc.
  • Ti165 Introduction
  • Ti165 Features
    • Ti165 Available Package Options
  • Ti165 Device Core Functional Description
    • Ti165 XLR Cell
    • Ti165 Embedded Memory
      • Ti165 True Dual-Port Mode
      • Ti165 Simple Dual-Port Mode
    • Ti165 DSP Block
    • Ti165 Clock and Control Network
      • Ti165 Clock Sources that Drive the Global and Regional Networks
      • Ti165 Driving the Global Network
      • Ti165 Driving the Regional Network
      • Ti165 Driving the Local Network
  • Ti165 Device Interface Functional Description
    • Ti165 Interface Block Connectivity
    • Ti165 GPIO
      • Ti165 Features for HVIO and HSIO Configured as GPIO
        • Ti165 Double-Data I/O
        • Ti165 Programmable Delay Chains
      • Ti165 HVIO
      • Ti165 HSIO
        • Ti165 HSIO Configured as GPIO
        • Ti165 HSIO Configured as LVDS
        • Ti165 HSIO Configured as MIPI Lane
      • Ti165 I/O Banks
    • Ti165 DDR DRAM Interface
    • Ti165 MIPI D-PHY
      • Ti165 MIPI RX D-PHY
      • Ti165 MIPI TX D-PHY
    • Ti165 Oscillator
    • Ti165 Fractional PLL
      • Ti165 Reference Clock Resource Assignments
      • Ti165 Programmable Duty Cycle
      • Ti165 Fractional Output Divider
      • Ti165 Spread-Spectrum Clocking
      • Ti165 Dynamic PLL Reconfiguration
      • Ti165 Dynamic Phase Shift
    • Ti165 Spread-Spectrum Clocking PLL
    • Ti165 Hardened RISC-V Block Interface
    • Ti165 Transceiver Interface
    • Ti165 Single-Event Upset Detection
    • Ti165 Internal Reconfiguration Block
  • Ti165 Security Feature
  • Ti165 Power Sequence
    • Ti165 Power-Up Sequence
    • Ti165 Power-Down Sequence
    • Ti165 Power Supply Current Transient
    • Ti165 Unused Resources and Features
  • Ti165 Configuration
    • Ti165 Supported Configuration Modes
  • Ti165 Characteristics and Timing
    • Ti165 DC and Switching Characteristics
    • Ti165 HSIO Electrical and Timing Specifications
    • Ti165 MIPI Electrical Specifications and Timing
      • Ti165 MIPI Reset Timing
    • Ti165 PLL Timing and AC Characteristics
    • Ti165 Configuration Timing
      • Ti165 JTAG Mode
      • Ti165 SPI Active Mode
      • Ti165 SPI Passive Mode
    • Ti165 Transceiver Specifications
  • Ti165 Pinout Description
    • Ti165 Configuration Pins
    • Ti165 Dedicated DDR Pinout
    • Ti165 Dedicated MIPI D-PHY Pinout
    • Ti165 Dedicated Transceiver Pinout
    • Ti165 Pin States
  • Ti165 Interface Floorplan
  • Ti165 Efinity Software Support
  • Ti165 Ordering Codes
  • Ti165 Revision History

Ti165 Characteristics and Timing

The following table shows the specification status for Ti165 packages.

Table 1. Package Status
Package Status
N484 Preliminary
C529 Preliminary
N900 Preliminary
N1156 Preliminary
  • Ti165 DC and Switching Characteristics
  • Ti165 HSIO Electrical and Timing Specifications
  • Ti165 MIPI Electrical Specifications and Timing
  • Ti165 PLL Timing and AC Characteristics
  • Ti165 Configuration Timing
  • Ti165 Transceiver Specifications

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