Support Center

Login Register Register a Kit

Home Documentation IP Cores

Example Design: Generating Multiple Output Frequencies from the T20 PLL with Dynamic Reference Clock Mode

This example design demonstrates how use a single PLL to generate three different output frequencies to three GPIO pins. The frequency of the three outputs changes with dynamic switching on the reference clock source. This design was compiled with Efinity® software v2018.4 and targets the Trion T20 BGA256 Development Board.

This content is locked and requires you to login before viewing more.

Please Wait!

Please wait...we are loading your content