Tz75 Revision History
| Date | Version | Description |
|---|---|---|
| October 2026 |
1.6 |
Updated the description for DLY_ENA, DLY_INC in Table 1. (DOC-2953) CDI17 corrected as CDI7 in dedicated configuration
pin description for SSU_N. (DOC-3074) Corrected the GPIO
or LVDS global clock resources on the right side for Figure 1. (DOC-3060) Characteristics and timing for N676 package are final.
(DOC-3001) Characteristics and timing for N484 package are final. (DOC-3280) Updated transceiver
specifications. (DOC-2974, DCO-3045) Added initial pin
state information and absolute maximum ratings for transceiver pins.
(DOC-2974) |
| April 2026 |
1.5
|
Updated number of HVIO pins available in N484 package. (DOC-2991) |
| March 2026 | 1.4 | Corrected AXI interrupt signal direction
in Hardened RISC-V Block Diagram. (DOC-2885) Updated
DSP block diagram; W register moved to after adder.
(DOC-2592)Updated Table 2. Updated Table 6. (DOC-2803)
Note added regarding reconfiguration to Tz75 Internal Reconfiguration Block.
Corrected definition for MIPI D-PHY signal
ERR_SOT_HS_LANn; SOT is start of transmission.
(DOC-2755)
Updated the presentation of the LPDDR4/4x resource information
in Table 2
to be consistent with other data sheets. (DOC-2814)
The Efinity software issues a warning (not
error) if you do not leave enough separation between GPIO and
LVDS or MIPI lane pins (see note). (DOC-2833)
Added pull-down resistor to HVIO figure Figure 1.
(DOC-2884)
Added transceiver analog power supply (VDDA_H_Q) specification.
(DOC-2910)
|
| October 2025 | 1.3 |
Added notes for Tz75 Single-Event Upset Detection.
(DOC-2602) Added N576 package. (DOC-2640) Changed minimum PMA Direct data rate. (DOC-2601)
Added note referring reader to AN 063: High-Speed
Transceiver Design Guidelines for PMA Direct RX
insertion loss guidelines. (DOC-2655)
Corrected Table 2. (DOC-2672)
Corrected Table 2.
Updated Figure 1 due to incorrectly labeled signals.
Updated Figure 4 due to incorrectly labeled signals.
Updated Table 10.
Renamed PLL TL to TL0 to align with Efinity in
Tz75 Reference Clock Resource Assignments.
Updated NSTATUS in Table 2.
|
| July 2025 | 1.2 |
Updated PLL maximum locked time in
Table 2 (DOC-2468)
Update number of core regional networks in
Tz75 Clock and Control Network. (DOC-2473)
Added N441 package
information.
Added Tz75 Transceiver Specifications. (DOC-2282)
Added RISC-V memory clock speed to Table 19. (DOC-2278)
Corrected link to Topaz DDR DRAM
Block User Guide. (DOC-2300)
|
| November 2024 | 1.1 |
Added DLYCLK GPIO signal. (DOC-2159)
Updated GPIO and LVDS interface pin names (IN to I and OUT to
O) to align with primitives. (DOC-2086)
Removed PLL IOFBK interface pin.
The SAMPLE/PRELOAD instruction is available after JTAG fuses
have been blown. (DOC-2225)
Fixed typo in Table 2. (DOC-2038)
Changed column name from Pins to Configuration
Functions in Table 2. (DOC-2038)
Added note after Table 2 directing the reader to the device pinout file. (DOC-2038)
Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)
Clarified HVIO and HSIO pin states during configuration and
when unused in user mode. (DOC-2041)
Added notes to the configuration timing and security feature
topics about not using SPI and JTAG at the same time.
(DOC-2047)
The transceiver supplies can be powered up in any sequence.
(DOC-2131)
Updated configuration timing and fuse programming waveforns.
(DOC-2156)
Corrected number of available transceiver banks.
(DOC-2205) |
October 2024 |
1.0 | Initial release. |