Efinix, Inc.
  • Tz75 Introduction
  • Tz75 Features
    • Tz75 Available Package Options
  • Tz75 Device Core Functional Description
    • Tz75 XLR Cell
    • Tz75 Embedded Memory
      • Tz75 True Dual-Port Mode
      • Tz75 Simple Dual-Port Mode
    • Tz75 DSP Block
    • Tz75 Clock and Control Network
      • Tz75 Clock Sources that Drive the Global and Regional Networks
      • Tz75 Driving the Global Network
      • Tz75 Driving the Regional Network
      • Tz75 Driving the Local Network
  • Tz75 Device Interface Functional Description
    • Tz75 Interface Block Connectivity
    • Tz75 GPIO
      • Tz75 Features for HVIO and HSIO Configured as GPIO
        • Tz75 Double-Data I/O
        • Tz75 Programmable Delay Chains
      • Tz75 HVIO
      • Tz75 HSIO
        • Tz75 HSIO Configured as GPIO
        • Tz75 HSIO Configured as LVDS
        • Tz75 HSIO Configured as MIPI Lane
      • Tz75 I/O Banks
    • Tz75 DDR DRAM Interface
    • Tz75 MIPI D-PHY
      • Tz75 MIPI RX D-PHY
      • Tz75 MIPI TX D-PHY
    • Tz75 Oscillator
    • Tz75 Fractional PLL
      • Tz75 Reference Clock Resource Assignments
      • Tz75 Programmable Duty Cycle
      • Tz75 Fractional Output Divider
      • Tz75 Spread-Spectrum Clocking
      • Tz75 Dynamic PLL Reconfiguration
      • Tz75 Dynamic Phase Shift
    • Tz75 Spread-Spectrum Clocking PLL
    • Tz75 Hardened RISC-V Block Interface
    • Tz75 Transceiver Interface
    • Tz75 Single-Event Upset Detection
    • Tz75 Internal Reconfiguration Block
  • Tz75 Security Feature
  • Tz75 Power Sequence
    • Tz75 Power-Up Sequence
    • Tz75 Power-Down Sequence
    • Tz75 Power Supply Current Transient
    • Tz75 Unused Resources and Features
  • Tz75 Configuration
    • Tz75 Supported Configuration Modes
  • Tz75 Characteristics and Timing
    • Tz75 DC and Switching Characteristics
    • Tz75 HSIO Electrical and Timing Specifications
    • Tz75 MIPI Electrical Specifications and Timing
      • Tz75 MIPI Reset Timing
    • Tz75 PLL Timing and AC Characteristics
    • Tz75 Configuration Timing
      • Tz75 JTAG Mode
      • Tz75 SPI Active Mode
      • Tz75 SPI Passive Mode
    • Tz75 Transceiver Specifications
  • Tz75 Pinout Description
    • Tz75 Configuration Pins
    • Tz75 Dedicated DDR Pinout
    • Tz75 Dedicated MIPI D-PHY Pinout
    • Tz75 Dedicated Transceiver Pinout
    • Tz75 Pin States
  • Tz75 Interface Floorplan
  • Tz75 Efinity Software Support
  • Tz75 Ordering Codes
  • Tz75 Revision History

Tz75 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Topaz FPGAs.
  • Tz75 Power-Up Sequence
  • Tz75 Power-Down Sequence
  • Tz75 Power Supply Current Transient
  • Tz75 Unused Resources and Features

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