Efinix, Inc.
  • Tz200 Introduction
  • Tz200 Features
    • Tz200 Available Package Options
  • Tz200 Device Core Functional Description
    • Tz200 XLR Cell
    • Tz200 Embedded Memory
      • Tz200 True Dual-Port Mode
      • Tz200 Simple Dual-Port Mode
    • Tz200 DSP Block
    • Tz200 Clock and Control Network
      • Tz200 Clock Sources that Drive the Global and Regional Networks
      • Tz200 Driving the Global Network
      • Tz200 Driving the Regional Network
      • Tz200 Driving the Local Network
  • Tz200 Device Interface Functional Description
    • Tz200 Interface Block Connectivity
    • Tz200 GPIO
      • Tz200 Features for HVIO and HSIO Configured as GPIO
        • Tz200 Double-Data I/O
        • Tz200 Programmable Delay Chains
      • Tz200 HVIO
      • Tz200 HSIO
        • Tz200 HSIO Configured as GPIO
        • Tz200 HSIO Configured as LVDS
        • Tz200 HSIO Configured as MIPI Lane
      • I/O Banks
    • Tz200 DDR DRAM Interface
    • Tz200 MIPI D-PHY
      • Tz200 MIPI RX D-PHY
      • Tz200 MIPI TX D-PHY
    • Tz200 Oscillator
    • Tz200 Fractional PLL
      • Tz200 Reference Clock Resource Assignments
      • Tz200 Programmable Duty Cycle
      • Tz200 Fractional Output Divider
      • Tz200 Spread-Spectrum Clocking
      • Tz200 Dynamic PLL Reconfiguration
      • Tz200 Dynamic Phase Shift
    • Tz200 Spread-Spectrum Clocking PLL
    • Tz200 Hardened RISC-V Block Interface
    • Tz200 Transceiver Interface
    • Tz200 Single-Event Upset Detection
    • Tz200 Internal Reconfiguration Block
  • Tz200 Security Feature
  • Tz200 Power Sequence
    • Tz200 Power-Up Sequence
    • Tz200 Power-Down Sequence
    • Tz200 Power Supply Current Transient
    • Tz200 Unused Resources and Features
  • Tz200 Configuration
    • Tz200 Supported Configuration Modes
  • Tz200 Characteristics and Timing
    • Tz200 DC and Switching Characteristics
    • Tz200 HSIO Electrical and Timing Specifications
    • Tz200 MIPI Electrical Specifications and Timing
      • Tz200 MIPI Reset Timing
    • Tz200 PLL Timing and AC Characteristics
    • Tz200 Configuration Timing
      • Tz200 JTAG Mode
      • Tz200 SPI Active Mode
      • Tz200 SPI Passive Mode
    • Tz200 Transceiver Specifications
  • Tz200 Pinout Description
    • Tz200 Configuration Pins
    • Tz200 Dedicated DDR Pinout
    • Tz200 Dedicated MIPI D-PHY Pinout
    • Tz200 Dedicated Transceiver Pinout
    • Tz200 Pin States
  • Tz200 Interface Floorplan
  • Tz200 Efinity Software Support
  • Tz200 Ordering Codes
  • Tz200 Revision History

Tz200 Power-Down Sequence

There is no specific power-down sequence for Tz200 FPGAs. However, the VQPS power supply must follow the specifications in Fuse Programming Requirements.

Parent topic: Tz200 Power Sequence

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