T85 PLL Timing and AC Characteristics

The following tables describe the PLL timing and AC characteristics.

Table 1. PLL Timing (C3, C4, and I4)
Symbol Parameter Min Typ Max Units
FIN1 Input clock frequency from core. 10 – 330 MHz
Input clock frequency from GPIO. 10 – 200 MHz
Input clock frequency from LVDS. 10 – 400 MHz
FOUT Output clock frequency. 0.24 – 500 MHz
FOUT Output clock frequency for PLL BR0 CLKOUT0 (DDR PHY input clock). 0.24 – 533 MHz
FVCO PLL VCO frequency for internal feedback mode. 500 – 1,600 MHz
PLL VCO frequency for local and core feedback mode 500 – 3,600 MHz
FPLL Post-divider PLL VCO frequency if all output divider values <= 64 62.5 – 1,800 MHz
Post-divider PLL VCO frequency if any of the output divider value > 64 62.5 – 1,400 MHz
FPFD Phase frequency detector input frequency. 10 – 100 MHz
Table 2. PLL Timing (C4L and I4L)
Symbol Parameter Min Typ Max Units
FIN1 Input clock frequency from core. 10 – 330 MHz
Input clock frequency from GPIO. 10 – 200 MHz
Input clock frequency from LVDS. 10 – 400 MHz
FOUT Output clock frequency. 0.24 – 500 MHz
FOUT Output clock frequency for PLL BR0 CLKOUT0 (DDR PHY input clock). 0.24 – 533 MHz
FVCO PLL VCO frequency for internal feedback mode. 500 – 1,600 MHz
PLL VCO frequency for local and core feedback mode 500 – 3,200 MHz
FPLL Post-divider PLL VCO frequency if all output divider values <= 64 62.5 – 1,600 MHz
Post-divider PLL VCO frequency if any of the output divider value > 64 62.5 – 1,200 MHz
FPFD Phase frequency detector input frequency. 10 – 100 MHz
Table 3. PLL AC Characteristics2
Symbol Parameter Min Typ Max Units
tDT Output clock duty cycle. 40 50 60 %
tOPJIT (PK - PK) 3 Output clock period jitter (PK-PK). – – 200 ps
tPLL_HLW PLL input clock from GPIO, HIGH/LOW pulse width. 2.25 – – ns
PLL input clock from LVDS, HIGH/LOW pulse width. 1.13 – – ns
tILJIT (PK - PK) Input clock long-term jitter (PK-PK) – – 800 ps
tLOCK PLL lock-in time. – – 0.5 ms
1 When using the Dynamic clock source mode, the maximum input clock frequency is limited by the slowest clock frequency of the assigned clock source. For example, the maximum input clock frequency of a Dynamic clock source mode from core and GPIO is 200 MHz.
2 Test conditions at 3.3 V and room temperature.
3 The output jitter specification applies to the PLL jitter when an input jitter of 20 ps is applied.