Functional Description

The AXI4-Stream Switch core consists of the following blocks:

Figure 1. AXI4-Stream Switch System Block Diagram

Each of the AXI4-stream ports carries the routing information through the TDEST (s_axis_tdest) signal. The router decodes the transaction destination. If there is more than a transaction is targeting the same destination simultaneously, the arbiter grants the master based on the selected arbitration scheme. The IP acknowledges the granted port by asserting the TREADY (s_axis_tready) of the granted port. The TREADY of other masters remains low. The granted master can now initiate the transaction.

There are multiple options for you to arbitrate the data transaction. You can set the IP to arbitrate based on:
  • TLAST signal—The master asserts the TLAST (s_axis_tlast) signal to indicate the end of a transfer
  • Maximum number of transfers—User defined number of transfers for each master
  • Number of LOW TVALID Cycles—User defined timeout counts for each master transaction