AXI4-Stream Switch Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example designs target the Titanium Ti60 F225 Development Board. The design demonstrates four master ports accessing two different slave ports through the AXI4-Stream Switch core. The AXI4-Stream Switch core routes the read and write data based on the TDEST information.

Figure 1. AXI4-Stream Switch Example Design

Table 1. Slave Ports Address Range
Slave	MIN	MAX
AXI_S0	0x00000000	0x00000001
AXI_S1	0x00000002	0x00000003

All four AXI master ports carry TDEST information between 0 to 3. Two of the four AXI masters (TDEST values 0 and 1) are routed to destination AXI_S0. While the other two (TDEST values 2 and 3) are routed to destination AXI_S1. Since there are two groups of master ports targeting different destination slave ports, the data transfer to the slave ports can happen simultaneously.

The Enable TLAST parameter is enabled in the example design. After the write operations are complete, the design compares the written data in the slave FIFOs to the expected data buffer and outputs the following on the development board LEDs:

Table 2. Example Design Output
Output		Description
LED D16 Blue	Test Done	Indicates the test is complete.
LED D16 Green	Test Pass	Indicates the written and read data are matched.
LED D16 Red	Test Fail	Indicates the written and read data are not matched.