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Sapphire RISC-V SoC

The Sapphire SoC is a cached soft RISC-V SoC that optionally includes a memory controller interface. The Sapphire SoC supports a variety of peripherals. You can choose which peripherals you want by configuring the SoC in the IP Manager. This core is similar to the open-source SaxonSOC, but it has been optimized for Trion® and Titanium FPGAs.

The Sapphire SoC incorporates a 1 to 4 32-bit RISC-V processors, 1 - 32 KB instruction cache, 1 - 32 KB data cache, 1 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 1 AXI slave). You can configure the operating frequency from 20 - 400 MHz (the actual performance is limited by the design's fMAX). The SoC includes 1 - 3 I²C peripherals, 1 - 3 UARTs, 1 - 3 user timers, 1 - 8 user interrupts, and 1 - 3 SPI masters. The SoC also features a floating-point unit (FPU) and Linux memory management unit (MMU).

The default configuration has up to 512-bit half-duplex and full-duplex AXI bus to communicate with the Efinix LPDDR4/4x controller or HyperRAM controller.

  • DDR controller—This core uses the Trion FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules. You can customize the SoC using the IP Manager in the Efinity  software.

Documentation

Sapphire Risc-V SoC Data Sheet

Sapphire Risc-V SoC Hardware and Software User Guide

Sapphire SoC Block Diagram

Sapphire SoC Multi-Core Block Diagram

Features

  • 1 - 4 (user selectable) VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 20 - 400 MHz system clock frequency
  • 1 - 512 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for DDR3, LPDDR4x or HyperRAM memories
    • Supports memory module sizes from 4 MB to 3.5 GB
    • User-configurable external memory bus frequency
    • 1 half duplex AXI3 interface or 1 full duplex AXI4 interface (up to 512-bits) to communicate with the external memory
    • 400 MHz DDR3 clock frequency, 800 Mbps
    • 1089 MHz LPDDR4x clock frequency, 2178 Mbps
    • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI master channels for user logic, data widths from 32 to 512
  • 1 AXI slave channel to user logic
  • Includes an optional multi-way instruction and Data Cache
  • Includes a floating point unit (FPU)
  • Includes an optional Linux memory management unit (MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as atomic and compressed
  • APB3 peripherals:
    • Up to 32 GPIOs
    • Up to 3 I2C masters
    • Clint timer
    • Platform-level interrupt controller (PLIC)
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rate
    • Up to 5 slave user peripherals
    • Up to 8 user interrupts

FPGA Support

The Sapphire SoC supports all Trion® FPGAs (except the T4) and all Titanium FPGAs, however, you may only be able to use some of the features in certain devices. For example, the DDR controller only works with FPGAs that have a hardened DDR controller block.

Titanium Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 1. Cacheless SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,048 7,664 44 4 377 2025.1
Ti60 F225 C4 (custom instruction) 7,192 7,716 44 4 392 2025.1
Table 2. Cacheless SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 4,503 3,120 12 4 377 2025.1
Ti60 F225 C4 (custom instruction) 4,530 3,151 12 4 396 2025.1
Table 3. Cached SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,627 8,110 56 4 410 2025.1
Ti60 F225 C4 (custom instruction) 7,635 8,152 56 4 372 2025.1
Ti60 F225 C4 (FPU) 14,113 12,232 77 13 296 2025.1
Ti60 F225 C4 (2 cores) 14,039 13,172 103 8 342 2025.1
Ti60 F225 C4 (3 cores) 18,035 15,521 127 12 314 2025.1
Ti60 F225 C4 (4 cores) 22,432 17,795 150 16 311 2025.1
Table 4. Cached SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 4,992 3,530 24 4 402 2025.1
Ti60 F225 C4 (custom instruction) 5,120 3,579 24 4 398 2025.1
Ti60 F225 C4 (FPU) 11,728 7,712 44 13 293 2025.1
Ti60 F225 C4 (2 cores) 11,374 8,302 62 8 335 2025.1
Ti60 F225 C4 (3 cores) 15,651 10,630 87 12 359 2025.1
Ti60 F225 C4 (4 cores) 19,966 12,882 110 16 348 2025.1
Table 5. Cacheless SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,388 2,797 14 0 399 2025.1
Ti60 F225 C4 (internal memory) 2,758 1,949 24 0 399 2025.1
Table 6. Cached SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,743 2,978 26 0 381 2025.1
Ti60 F225 C4 (internal memory) 3,078 2,124 36 0 420 2025.1

Trion Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 7. Cacheless SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,036 7,816 48 4 113 2025.1
T120 F324 (custom instruction) 7,115 7,858 48 4 108 2025.1
Table 8. Cacheless SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 4,575 3,258 16 4 116 2025.1
T120 F324 (custom instruction) 4,632 3,300 16 4 117 2025.1
Table 9. Cached SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,555 8,253 67 4 123 2025.1
T120 F324 (custom instruction) 7,620 8,302 67 4 112 2025.1
T120 F324 (FPU) 14,683 12,605 80 13 88 2025.1
T120 F324 (2 cores) 14,148 13,456 109 8 94 2025.1
T120 F324 (3 cores) 18,473 15,928 136 12 87 2025.1
T120 F324 (4 cores) 22,313 18,334 162 16 93 2025.1
Table 10. Cached SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 5,032 3,678 35 4 115 2025.1
T120 F324 (custom instruction) 5,104 3,723 35 4 114 2025.1
T120 F324 (FPU) 12,050 8,074 47 13 88 2025.1
T120 F324 (2 cores) 11,631 8,575 68 8 99 2025.1
T120 F324 (3 cores) 15,721 11,034 96 12 102 2025.1
T120 F324 (4 cores) 19,702 13,425 122 16 86 2025.1
Table 11. Cacheless SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 3,310 2,804 18 0 113 2025.1
T120 F324 (internal memory) 2,722 1,963 40 0 112 2025.1
Table 12. Cached SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 3,707 3,025 37 0 111 2025.1
T120 F324 (internal memory) 3,333 2,171 59 0 125 2025.1

Topaz Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 7. Cacheless SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 7,048 7,664 44 4 242 2025.1
Tz110 J484 C3 (custom instruction) 7,192 7,716 44 4 276 2025.1
Table 8. Cacheless SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 4,503 3,120 12 4 231 2025.1
Tz110 J484 C3 (custom instruction) 4,530 3,151 12 4 254 2025.1
Table 9. Cached SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 7,627 8,110 56 4 273 2025.1
Tz110 J484 C3 (custom instruction) 7,635 8,152 56 4 263 2025.1
Tz110 J484 C3 (FPU) 14,113 12,232 77 13 197 2025.1
Tz110 J484 C3 (2 cores) 14,039 13,172 103 8 218 2025.1
Tz110 J484 C3 (3 cores) 18,635 15,521 127 12 209 2025.1
Tz110 J484 C3 (4 cores) 22,432 17,595 150 16 208 2025.1
Table 10. Cached SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 4,992 3,530 24 4 246 2025.1
Tz110 J484 C3 (custom instruction) 5,120 3,579 24 4 264 2025.1
Tz110 J484 C3 (FPU) 11,728 7,712 44 13 202 2025.1
Tz110 J484 C3 (2 cores) 11,374 8,302 62 8 228 2025.1
Tz110 J484 C3 (3 cores) 15,651 10,630 87 12 227 2025.1
Tz110 J484 C3 (4 cores) 19,966 12,882 110 16 224 2025.1
Table 11. Cacheless SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (external memory) 3,388 2,797 14 0 259 2025.1
Tz110 J484 C3 (internal memory) 2,758 1,949 24 0 269 2025.1
Table 12. Cached SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (external memory) 3,743 2,978 26 0 271 2025.1
Tz110 J484 C3 (internal memory) 3,078 2,124 36 0 279 2025.1


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