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Sapphire RV64 SoC

The Sapphire RV64 SoC is a configurable and cached soft RISC-V SoC that optionally includes a DDR DRAM controller interface. The Sapphire RV64 SoC supports a variety of peripherals. You can choose which peripherals you want by configuring the SoC in the IP Manager. This core is similar to the open-source VexiiRiscv, but it has been optimized for Trion® and Titanium FPGAs.

The Sapphire RV64 SoC incorporates a 1 to 4 64-bit RISC-V processors that have an instruction cache and data cache with up to 8-ways, each way is equipped with 4 KB, 64 KB to 512 KB 8-ways L2 cache, 4 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals, and 2 AXI slaves and 2 AXI masters). You can configure the operating frequency from 20 - 400 MHz (the design's fMAX limits the actual performance).

Other optional CPU micro-architectures, such as floating-point unit (FPU), a dynamic branch predictor, software and hardware prefetchers, custom instruction interfaces, physical memory protection, and an SV39 memory management unit (MMU), can be configured with the IP manager.

The SoC includes a CLINT timer, a platform local interrupt controller, a watchdog timer, 1 - 5 I²C peripherals, 1 - 3 UARTs, 1 - 3 user timers, 1 - 8 user interrupts, and 1 - 3 SPI masters. The default configuration supports a half-duplex and a full-duplex AXI bus with up to 512 bits to communicate with the Efinix LPDDR4x controller, DDR3 controller, or HyperRAM controller.

The default configuration has up to 512-bit half-duplex and full-duplex AXI bus to communicate with the Efinix LPDDR4/4x controller or HyperRAM controller.

  • DDR controller—This core uses the Trion or Titanium FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and reinitializes the Trion or Titanium FPGA's DDR interface, which includes the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules. You can customize the SoC using the IP Manager in the Efinity software.

Documentation

Efinity RISC-V Embedded Software IDE

Sapphire RV64 SoC Data Sheet

Sapphire RV64 SoC User Guide

Sapphire RV64 SoC Block Diagram

Features

  • 1 - 4 (user selectable) VexiiRiscv processor(s) with 7 pipeline stages (fetch, align-decompress, decode, issue, execute, memory, and writeback)
  • Interrupts and exception handling with machine and supervisor modes.
  • 20 - 400 MHz system clock frequency
  • 4 - 512 KB on-chip RAM with boot loader for SPI flash
  • Debug:
    • Supports standard RISC-V debug specification
    • Up to 4 hardware breakpoints
    • Up to 4 performance counters
    • Supports co-debug with the FPGA debugger
  • Memory controller for DDR3, LPDDR4x, or HyperRAM memories, supports memory module sizes from 4 MB to 8 GB:
    • User-configurable external memory bus frequency:
      • 1 half-duplex AXI3 interface (up to 512 bits) or 1 full-duplex AXI4 interface (up to 512 bits) to communicate with the external memory
      • 400 MHz DDR3 clock frequency, 800 Mbps
      • 1,600 MHz LPDDR4x clock frequency, 3,200 Mbps
      • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI slave channels for user logic, data widths from 32 to 512-bits, with memory coherency
  • 1 AXI master channel to user logic
  • Includes a multi-way L1 instruction and data cache
  • Includes an optional L2 cache
  • Includes an optional branch predictor
  • Includes an optional physical memory protection unit
  • Includes an optional hardware and software pre-fetcher
  • Includes a floating-point unit (FPU)
  • Includes an optional Linux memory management unit (SV39 MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as single and double-digit floating point, atomic, compressed, bit manipulation, and cache block management.
  • I/O peripherals:
    • Up to 32 GPIOs
    • Up to 5 I2C masters
    • Clint timer
    • Platform-level interrupt controller (PLIC)
    • Watchdog timer
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rates
    • Up to 5 slave user peripherals with APB3 interface
    • Up to 8 user interrupts

FPGA Support

The Sapphire SoC supports all Trion® FPGAs (except the T4) and all Titanium FPGAs, however, you may only be able to use some of the features in certain devices. For example, the DDR controller only works with FPGAs that have a hardened DDR controller block.

Resource Utilization and Performance

The Sapphire RV64 SoC is configurable. These tables show the resource usage for various configurations.

Basic L2:
  • Single-core RV64, with 64 KB L2 cache and 1-way 4 KB data and instruction cache.
  • RV64 I, M, A, and C extensions enabled.
  • 256-bit width AXI4 for external memory, 1 SPI, and 1 UART.
Basic L1:
  • Same configurations as Basic L2, but excluding the L2 cache.
Advanced L2:
  • Single-core RV64, with 64 KB L2 cache, 1-way 4 KB data, and instruction cache.
  • All available extensions enabled, except for Zicbom.
  • All extended features enabled.
  • 256-bit width AXI4 for external memory, 1 SPI, and 1 UART.
Advanced L1:
  • Same configuration as Advanced L2, but excluding the L2 cache.

Titanium Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 1. Titanium Ti375 C529 Resource Utilization and Performance
Configuration Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,258 12,624 188 17 278 2026.1
Basic L1 10,740 9,024 91 17 271 2026.1
Advanced L2 27,250 17,869 225 17 252 2026.1
Advanced L1 23,838 14,253 128 17 250 2026.1
Table 2. Topaz Tz170 J484 Resource Utilization and Performance
Configuration Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,258 12,624 188 17 170 2026.1
Basic L1 10,740 9,024 91 17 176 2026.1
Advanced L2 27,250 17,869 225 17 167 2026.1
Advanced L1 23,838 14,253 128 17 164 2026.1
Table 3. Trion T120 F324 Resource Utilization and Performance
Configuration Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,309 12,468 259 17 77 2026.1
Basic L1 10,741 9,046 98 17 77 2026.1
Advanced L2 26,894 17,903 303 17 65 2026.1
Advanced L1 23,612 14,355 142 17 65 2026.1


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