Note: the Ruby SoC is end of life in the Efinity software v2022.1.226. This SoC is replaced by the Sapphire SoC.

The Ruby SoC incorporates a 32-bit RISC-V processor, 4 KB instruction cache, 4 KB data cache, 4 KB of on-chip RAM, and a variety of peripherals (including 2 APB3 slave peripherals and 1 AXI slave). The SoC includes 3 I²C peripherals and a 128-bit half-duplex AXI bus to communicate with the Efinix DDR controller core. This core uses the Trion® FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and re-initializes the Trion® FPGA's DDR interface as well as the DDR module(s)).

Ruby SoC Block Diagram

Features

• VexRiscv processor with 5 pipeline stages (fetch, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 4 KB data cache
  • 4 KB instruction cache
• 10 - 350 MHz system clock frequency
• 4 - 512 KB on-chip RAM with boot loader for SPI flash
• DDR controller
  • 100 MHz DDR memory bus frequency
  • 128-bit AXI data width
  • 3.5 GB memory module
  • 400 MHz DDR clock frequency, 800 Mbps
• 1 AXI master channel to access the DDR memory
• 1 AXI slave channel to user logic
• APB3 peripherals:
  • 16 GPIOs
  • 3 I²C masters and slaves
  • Machine timer
  • PLIC
  • 3 SPI flash masters with a maximum clock frequency of 25 MHz
  • 2 UARTs with 115,200 baud rate
  • 2 slave user peripherals

FPGA Support

The Ruby SoC supports T35, T55, T85, and T120 Trion® FPGAs.

Trion Resource Utilization and Performance

FPGA	Logic Utilization (LUTs)	Memory Blocks	fMAX (MHz)	Language	Efinity Version
T120 BGA324 C4	11,807	68	SoC: 104 Memory: 112	Verilog HDL	2021.1