Opal RISC-V SoC
Note: the Opal SoC is end of life in the Efinity software v2022.1.226. This SoC is replaced by the Sapphire SoC.
The Opal SoC incorporates a 32-bit RISC-V processor, 4 KB instruction cache, 4 KB data cache, 4 KB of on-chip RAM, and a variety of peripherals (including 1 APB3 slave peripherals).
Opal SoC Block Diagram
Features
- VexRiscv processor with 5 pipeline stages (fetch, decode, execute, memory, and write back), interrupts and exception handling with machine mode
- 10 - 300 MHz or 20 MHz (T8 BGA81 only) system clock frequency
- 4 KB on-chip RAM with boot loader for SPI flash
- APB3 peripherals:
- 8 GPIOs
- 1 I2C master and slave
- Machine timer
- PLIC
- 1 SPI flash master with a maximum clock frequency of 25 MHz (10 MHz maximum for T8 BGA81 only)
- 1 UART with 115,200 baud rate
- 1 slave user peripheral
FPGA Support
The Opal SoC supports all Titanium FPGAs and Trion® FPGAs (except the T4).
Titanium Resource Utilization and Performance
| FPGA | Logic/Adders | FlipFlops | Memory Blocks | DSP48 Blocks | fMAX (MHz) | Language | Efinity Version |
|---|---|---|---|---|---|---|---|
| Ti60 F225 C3 (min) | 4,303 | 2,374 | 18 | 4 | 160 | Verilog HDL | 2021.1 |
Trion Resource Utilization and Performance
| FPGA | Logic Utilization (LUTs) | Memory Blocks | fMAX (MHz) | Language | Efinity Version |
|---|---|---|---|---|---|
| T20 BGA256 C4 | 5,299 | 18 | 87 | Verilog HDL | 2021.1 |
| T8 BGA81 C2 | 5,196 | 16 | SoC: 23.793 | Verilog HDL | 2019.3 |