The PLL Dynamic Reconfiguration core allows users to change the PLL settings on an Efinix FPGA, without changing the settings in the Interface Designer, recompiling, and regenerating the bitstream file. This IP core provides an efficient way to change the PLL settings on the fly after initial boot-up, without having to reconfigure the FPGA.

The PLL Dynamic Reconfiguration core is positioned between the user's logic and the PLL to facilitate the dynamic reconfiguration scheme. There are 2 versions of PLL Dynamic Reconfiguration to match the Fractional PLLs:

• PLL Dynamic Reconfiguration[product-core] core V1 pairs with Fractional PLL V1.
• PLL Dynamic Reconfiguration[product-core] core V2 pairs with Fractional PLL V2.

PLL Dynamic Reconfiguration Core V1 Block Diagram with Fractional PLL V1:

PLL Dynamic Reconfiguration Core V2 Block Diagram with Fractional PLL V2:

Features

The PLL Dynamic Reconfiguration core includes the following features:

• Allow maximum 85 PLL settings to be stored and reconfigure the PLL
• Allows the FPGA to revert to the original PLL settings in the bitstream file. (1)
• Single_CFG and multi_CFG mode.

Note: 1) The original PLL settings are also known as Peripheral Configuration Register (PCR) settings.