The MIPI D-PHY is a scalable physical layer for interfacing various components such as cameras and displays to host devices. The MIPI D-PHY TX Controller V2 core allows you to control and configure the MIPI D-PHY TX interface. You use the MIPI D-PHY TX Controller V2 core with the Titanium HSIO pins configured as MIPI TX lanes to build a custom MIPI interface.

MIPI D-PHY TX Controller V2 Block Diagram

Features

• 1, 2, 4, or 8 configurable data lanes
• Unidirectional (CSI) and bidirectional (DSI) data lane
• High-speed (HS) mode for data communication and low-power (LP) mode for data communication
• 100 MHz core clock frequency
• PHY Protocol Interface (PPI) that supports 8-bit or 16-bit high-speed transmitting data bus
• Supports data rate: (1)
  1. PPI 8-bit—Up to 1.5 Gbps (HS mode byte clock frequency from 10 MHz up to 187 MHz)
  2. PPI 16-bit—Up to 2.5 Gbps (HS mode byte clock frequency from 5 MHz up to 156 MHz)
• Continuous HS byte clock and discontinuous HS byte clock
• Supports D-PHY-only, D-PHY with CSI, or D-PHY with DSI
• Supports end-of-transmission error, start-of-transmission sync error, control error, and LP escape error
• Supports initial skew calibration after initialization is completed
• Supports all Titanium and Topaz FPGAs

Note: 1) The maximum data rate of IP depends on the devices. Refer to the respective device data sheet for more accurate information.