The MIPI DSI specifies the physical link between the chip and display in devices such as smartphones, tablets, AR/VR headsets, and connected cars (1). It defines a serial bus and a communication protocol between the host (the source of the image data) and the destination (e.g., display peripherals). The MIPI 2.5G DSI TX Controller core implements the MIPI DSI interface in the FPGA and allows you to configure the related parameters.

Note: (1) MIPI Alliance.

MIPI DSI RX Controller Block Diagram

Features

• Supports 1, 2, and 4 data lanes
• Supports continuous or discontinuous clock mode
• HS mode byte clock frequency from 5 Mhz to 156.25 Mhz (80 Mbps to 2,500 Mbps data rate) (2)
• 16-bit HS mode data width
• Includes AXI4-Lite interface for register access
• Error correction code (ECC) generation for packet headers
• Cyclic redundancy check (CRC) generation for data bytes
• Supports non-burst with sync pulses, non-burst with sync events, and burst mode
• Supports end of transmission packet
• Supports commands transmission in HS or LP mode
• Supports initial auto-skew calibration
• Supports PPI interface

Note: (2) The maximum data rate of IP depends on the devices. Refer to the respective device data sheet for more accurate information.