The MIPI CSI-2 interface, which defines a simple, high-speed protocol, is the most widely used camera interface for mobile. Adding a MIPI interface to an FPGA creates a powerful bridge to transmit or receive high-speed video data easily to/from an application processor. The MIPI 2.5G CSI-2 TX Controller core allows you to perform complex video and image processing as a part of a complete system solution with a data rate of up to 2.5 Gbps. The MIPI 2.5G CSI-2 TX Controller uses the hard MIPI D-PHY blocks in supported Titanium FPGAs.

MIPI 2.5G CSI-2 RX Controller Block Diagram

Features

• Configurable data lanes: 1, 2, or 4
• High-speed (HS) mode and Low-power (LP) mode
• Arbitrary number of payload data bytes
• IP core clock frequency at 100 MHz
• HS mode byte clock frequency from 25 to 156.25 MHz (400 to 2,500 Mbps data rate)
• Continuous HS mode byte clock and discontinuous HS mode byte clock
• 16-bit HS mode data width
• Pixel format:
  • RAW: RAW6, RAW7, RAW8, RAW10, RAW12,RAW14
  • RGB: RGB444, RGB555, RGB565, RGB888
  • YUV: YUV420 8-bit (legacy), YUV420 8-bit, YUV420, 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit
• User defined 8-bit data types
• Generic 8-bit long packet
• Null, blank and embedded 8-bit non image data
• PPI interface
• Generic frame mode and accurate frame mode
• Supports end of transmission error, start of transmission sync error, control error & LP escape error
• Supports control status register (CSR) for status and error assertion accessed through AXI4-Lite interface
• Supports initial auto-skew calibration and self-periodic skew calibration
• Supports Ti90, Ti120, and Ti180 Titanium FPGAs