The core is a configurable and synthesizable Verilog module that implements the Test Access Port (TAP) state machine based on the IEEE Std. 1149.1. This IP core is intended to work in conjunction with the JTAG to SPI Flash Bridge core for flash programming, and with Efinity’s Debugger for debugging purposes, particularly in scenarios where the 's hard JTAG controller is disabled for security reasons.

Note: This core is a soft JTAG implementation and is not a hard JTAG controller in the FPGA. Thus, it only supports the following instructions:

• IDCODE
• JTAG_USER1
• JTAG_USER2
• JTAG_USER3
• JTAG_USER4
• BYPASS

JTAG Core Block Diagram

Features

The JTAG core includes the following features:

• Supports IEEE Std. 1149.1 for TAP state machine (FSM) behavior
• Configurable IDCODE instruction and value
• Supports up to 4 JTAG User TAPs
• Customizable BYPASS instruction