The Divider_2 core creates a circuit for integer division based on Radix-2 restoring division, which enables a fractional or integer remainder to be generated.

Divider_2 Core Block Diagram

Features

The Divider_2 core includes the following features:

• Supports quotient output with integer or fractional remainder
• Supports numerator data widths of 1 to 64 bits
  • To reduce clock latency by one clock cycle, the unsigned reciprocal (1/X) function only support a data width of 1 bit.
• Supports denominator data widths of 2 to 64 bits
• Supports configurable pipeline latency to trade off FPGAresources versus throughput
• Supports signed and unsigned data representation format for both the numerator and denominator:
  • Two's complement signed format
• Supports signed and unsigned reciprocal (1/X) function
• Supports independent numerator, denominator, and fractional bit widths
• Fully registered outputs