The 8b/10b PCS core provides transmit 8b/10b encoding and receive 8b/10b decoding for FPGA transceiver-based serial links. The core is intended to be used between user logic or a higher-layer protocol controller and the FPGA high-speed transceiver interface. 

On the transmit path, the core converts 8-bit data and control characters into 10-bit encoded symbols with running disparity control. On the receive path, the core performs comma-based word alignment, decodes received 10-bit symbols into 8-bit data and control characters, and reports decoder errors.

This release provides general-purpose 8b/10b PCS functions. Protocol-specific functions such as link initialization and protocol state machines must be implemented outside the core unless explicitly stated as supported in this user guide.er layer protocol. 

Deskew FIFO and elastic buffer functions are planned for a future release and are not supported in this release.

Note:  Bonded lane operation in this release groups the selected lanes under a common configuration and clocking arrangement. The bonded lanes use the same interface width, operating mode, comma patterns, etc. In bonded configurations, the Lane 0 PCS clock is applied internally to all lanes in the bonded group, as mentioned in the Functional Description of the  8b/10b PCS Core User Guide. If lane-to-lane alignment is required, user logic must implement their own deskew FIFO.

8b/10b PCS Core Block Diagram

Features

The 8b/10b PCS core includes the following features:

• Supports transceiver interface widths of 20 bits and 40 bits
• Supports x1, x2, and x4 lane bonding modes, with x8 bonding mode available only in RX_FIFO mode
• Supports independent TX and RX data path per enabled lane
• Supports transmit 8b/10b encoding with running disparity control
• Supports receive comma-based word alignment
• Supports receive 8b/10b decoding with data/control character indication 
• Detects invalid code-groups and running disparity errors
• Replaces the decoded payload with 8'hFE when a decode error is detected 
• Provides configurable 10-bit comma characters for word alignment
• Provides configurable word aligner lock threshold
• Supports lock-loss detection based on receive error-symbol count
• Provides optional pipeline registers for timing closure