Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 2. Titanium Resource Utilization and Performance
FPGA Mode Logic and Adders Flip-flops Memory Blocks DSP Blocks fMAX (MHz)1 Efinity® Version2
Ti60 F225 C4 arcsin and arccos 1,279 132 0 0 290 2022.2
arctan 984 96 0 0 333
exp 1,990 231 0 2 92
ln 1,186 168 0 2 319
sin and cos 1,474 169 0 0 335
sinh and cosh 2,364 217 0 2 93
sqrt 1,667 169 0 2 273
tanh 1,740 228 0 0 321
Table 3. Trion® Resource Utilization and Performance
FPGA Mode Logic Utilization (LUTs) Registers Memory Blocks Multipliers fMAX (MHz)1 Efinity® Version2
T20 BGA256 C4 arcsin and arccos 1,279 132 0 0 84 2022.2
arctan 984 96 0 0 86
exp 2,123 237 0 2 28
ln 1,189 168 0 2 89
sin and cos 1,474 169 0 0 103
sinh and cosh 2,287 222 0 2 26
sqrt 1,548 168 0 2 82
tanh 1,523 229 0 0 88
1 Using default parameter settings.
2 Using Verilog HDL.