Topaz Tz100 FPGAs

The Tz100 FPGA features the high-density, low-power Efinix® Quantum® compute fabric wrapped with an I/O interface. This FPGA has a variety of features, such as a hardened RISC-V block, transceivers (includng PCIe® Gen 3x4), LPDDR4 DRAM controller, and MIPI D-PHY.

The quad-core hardened RISC-V block has a 32-bit CPU featuring the ISA RISCV32I with M, A, C, F, and D extensions, and six pipeline stages. You utilize the hardened RISC-V block by instantiating the Sapphire High-Performance SoC, combining the speed and efficiency of a hardened RISC-V block with the flexibility of peripherals in soft logic.

The full-duplex transceiver supports the PCIe 3.0, Ethernet SGMII, and Ethernet 10GBase-KR protocols as well as a PMA direct mode with data rates up to 12.5G.

Tz100 FPGAs include a hardened MIPI D-PHY controller, which you can use with MIPI CSI-2 and DSI controller IP cores to create multi-camera, high definition vision systems, edge computing, and hardware acceleration systems. Additionally, these FPGAs have a hardened DDR DRAM controller block that supports the LPDDR4 DRAM interface.

• Fabricated on a 16 nm process
• Quad-core hardened RISC-V block
• PCIe® Gen3 (8G)
• 10 Gigabit Ethernet
• SGMII
• PMA direct (up to 12.5G)
• High-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
• High-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.3 Gbps; and also operate as MIPI lanes at 1.3 Gbps
• MIPI D-PHY hard IP with speeds up to 2 Gbps
• LPDDR4 PHY (supporting x16 or x32 DQ widths) with hardened memory controller
• Device configuration options including a standard SPI and JTAG interfaces
• Fully supported by the Efinity® software, an RTL-to-bitstream compiler

Applications

Robotics, multi-axis motion controllers, keyboard, video, and mouse (KVM), and machine vision.