Titanium™ Ti125 FPGAs

The Ti125 FPGA features the high-density, low-power Efinix® Quantum® compute fabric wrapped with an I/O interface in a small footprint package for easy integration. With integrated SEU detection and correction, Ti125 FPGA provides robust protection against soft errors, enabling reliable, high-accuracy processing and uninterrupted operation in demanding environments.

With ultra-low power consumption, Ti125 FPGA is ideal for always-on applications, while enhanced configurable high-speed I/O with support for up to 2.5 Gbps MIPI enables seamless connectivity to multiple high-speed cameras.

• Fabricated on a 16 nm process
• High-voltage I/O (HVIO)—support single-ended LVTTL and LVCMOS I/O standards.
• High-speed I/O (HSIO)—support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.5 Gbps; and also operate as MIPI lanes at 1.5 Gbps
• Enhanced high-speed I/O (HSIO2) —support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.8 Gbps; and also operate as MIPI lanes at 2.5 Gbps
• Single-event upset (SEU) detection and correction feature
• Device configuration options including a standard SPI and JTAG interfaces
• Fully supported by the Efinity® software, an RTL-to-bitstream compiler

Applications

Autonomous vehicles, medical imaging, smart surveillance, advanced industrial automation, AI, IoT and sensor fusion.