Last updated: November 18, 2024


*** Upgrading from previous Efinity versions ***

Previously generated data files from Efinity compilations (such as old 
synthesis, place and route output files) may not be compatible with this
version of Efinity software.  Full recompilation is recommended.


*** Description ***

This is a release package of the Efinity tools for compiling and simulating
designs targeting the Efinix programmable logic devices.


*** New features in Efinity 2024.2 ***

   -- Introduces Efinity support for the Topaz FPGA family
       -- Optimized for low power, high volume, and high performance
       -- New devices:
           -- Tz50F100, Tz50F225, Tz50F256
           -- Tz110J361, Tz110G400, Tz110J484
           -- Tz170J361, Tz170G400, Tz170J484
       -- Supported speed grades include C2/C3/I2/I3
       -- Bitstreams enabled for Tz50F100, Tz50F225, Tz50F256
   -- [Titanium] Adds support for Ti135N484, Ti85N484 devices [DEVINFRA-992]
   -- Introduces unified design to Efinity flow, allowing user to instantiate or
      infer basic interface blocks directly in user's design RTL
      -- Supported for all device families
      -- Functions in tandem with Efinity's Interface Designer and Efinity's
         logic synthesis tool
      -- Unified simulation support included for basic periphery blocks such as
         GPIO, PLL
      -- Adds synthesis inferencing for basic I/O elements including I/O
         buffers and I/O registers
   -- [Titanium] Various improvements in synthesis, placement, and routing
       -- ~5% improved fmax compared to Efinity 2024.1
       -- ~40% reduction in compiler peak memory compared to Efinity 2024.1
   -- Supports new SDC commands
       -- "check_timing" analyzes the design and SDC constraints,
          warning user over SDC clock assignment and I/O constraint issues.
       -- "report_cdc" specifically analyzes the design for cross-domain
          clocking paths.
   
   
   
*** Fixed issues in Efinity 2024.2 ***

   Note:  this list is not comprehensive
   -- Efinity GUI now requires the top-level project module/entity name
      to be set [GUI-1265]
   -- [Titanium] Adds more flexible options for clock source selection
      in PMA Direct bonding modes [PT-2557]
   -- [Titanium] Adds PCI-e requirement for connected APB clock [PT-2543]
   -- Fixes non-determinism issue in synthesis related to optimize-adder-tree
      option [SYN-883]
   -- [Titanium/Topaz] Updates HSIO-based MIPI slowclk vs fastclk phase
      shift rules if the data rate is 1 Gbps or higher [PT-2435]
      -- Existing MIPI designs may need to update PLL settings to avoid
         compilation errors
   -- [Titanium/Topaz] Updates generated SDC constraints for negedge triggered
      HSIO dynamic input delay pins [PT-2541]
   -- [Titanium/Topaz] Updates Security Key Generator tool's JTAG disabling
      options [PROG-563]
   -- Adds optional comparator display to Debugger's VIO probes [HD-360]
   -- Adds setup/hold timing modeling to CE pin of GBUFCE primitive [VPR-854]






*** Contents ***

arch/           : Architecture description files
bin/            : Executable binaries for synthesis, place & route, etc.
debugger/       : Hardware Debugger Python libraries
doc/            : Documentation
ipm/            : IP Manager Python libraries
lib/            : Dynamic libraries
log/            : GUI output logs
pgm/            : Programmer Python libraries
project/        : Example projects
python311/      : Python installation (Windows only)
pt/             : Interface Designer Python libraries
scripts/        : Helper scripts for running different FPGA flows
sim_models/     : Functional simulation models for Efinity primitives
security/       : Tools for bitstream security
tcl_packages/   : Tcl library files, init scripts
license*.txt    : License files
readme.txt      : This file



*** Setup Requirements ***

This release has been verified to run on several mainstream 64-bit desktop
Linux distributions.  Efinix recommends Ubuntu 18.04 x86-64 (or later 
versions) or Red Hat Enterprise 8.8 x86-64 (or later versions).

The Efinity software is also supported for Microsoft Windows 10 64-bit 
(or more recent versions).

Linux Requirements:
    -- 64-bit OS installed
    -- The Efinity GUI tool requires X11 installed.

Windows Requirements:
    -- 64-bit OS installed
    -- MSVC 2019 x64 runtime distributable installed.  This can be freely
       downloaded and installed from 
       https://docs.microsoft.com/en-us/cpp/windows/latest-supported-vc-redist?view=msvc-170


Hardware Recommendations:
    -- x86-64 processor, at least dual-core
    -- machine memory requirements may vary depending on the size of Efinix
       device and customer design
       
       ---------------------------------------------------------------
       FAMILY      DEVICE                Minimum memory recommendation
       ---------------------------------------------------------------
       Trion       T4/T8/T13/T20/T35     8 GB
       Trion       T55/T85/T120          16 GB
       Titanium    Ti35/Ti60             8 GB
       Titanium    Ti90/Ti120/Ti180      16 GB
       Titanium    Ti165/Ti240/Ti375     16 GB
       Titanium    Ti85/Ti135            16 GB
       Topaz       Tz50                  8 GB
       Topaz       Tz110/Tz170           16 GB
       Topaz       Tz200/Tz325           16 GB
       ---------------------------------------------------------------

*** Third Party Simulator ***

The Efinity tools do not include third party simulators, nor any
explicit tool integration with third party simulators.  However,
three different simulators have been verified to work with Efinity-generated
Verilog netlist files:

    -- Incisive Enterprise Simulator (R).  Incisive has robust
       Verilog HDL language support as well as excellent simulation runtime.  
       See Cadence documentation for details.
    -- QuestaSim (R).  QuestaSim has robust Verilog HDL language support 
       as well as the best simulation runtime.  See
       Mentor Graphics documentation for details.
    -- iVerilog.  For small designs or prototyping, this free open-source
       utility may fit your needs.  iVerilog is available in Ubuntu, CentOS,
       and other Linux repositories, or freely downloadable from the web.
       Windows versions can be downloaded from http://bleyer.org/icarus/

To simulate a post-synthesis (or later compiler stage) Verilog HDL netlist
produced by the Efinity tools, please include the following library path
as a resource in your third party simulator:

<Efinity top-level path>/sim_models/verilog


       
*** Installation ***

Linux installation:

    Simply unzip/untar the efinity package into a suitable user directory.
    
        > tar -xjvf efinity-<version>.tar.bz2
        
    Optional installation:

        To use the Efinity programmer, you need to install the included
        USB UDEV device manager.  (i.e., /etc/udev/rules.d/...)  Run the
        following command with root privilege:

        > sudo ./bin/install_usb_driver.sh


        You can run the following script to install a shortcut in
        your Desktop directory.  (i.e., ~/Desktop)

        > ./bin/install_desktop.sh



Windows installation:

    Double-click on the efinity-<version>.msi installer package and follow
    the on-screen instructions.

    Optional installation:

        To use the Efinity programmer, you need to install the appropriate
        USB drivers. Efinix recommends using the Zadig software for this purpose.
        
        1. Download and install the Zadig software (version 2.7 or later) from
           zadig.akeo.ie.
        2. Open the Zadig software.
        3. Choose Options > List All Devices.
        4. Repeat the following steps for each interface. The interface names end
           with (Interface N), where N is the channel number.
           -- Select libusb-win32 in the Driver drop-down list.
           -- Click Replace Driver.


*** Quick start ***

To launch the Efinity tool, simply double-click on the Efinity desktop
icon.  To launch the Efinity tool from the command line, simply run:

    Linux:
        > ./bin/efinity_sh.sh

    Windows:
        > bin\setup.bat --run




*** Command line scripting setup ***

To run the Efinity tools from command line scripting interface, you must
setup some environment variables.  Run the following command to set up your shell
environment:

    Linux:
        > source bin/setup.sh

    Windows:
        > bin\setup.bat

Note that this will also update your local PATH variable to include the
Efinity tools directory.




*** Command-Line Scripting Quick Start ***

The Efinity compiler tools can be invoked using the efx_run.py python3
script in the $EFINITY_HOME/scripts directory, after command line scripting
setup has been completed.

Example:

    Linux:
        > cd $EFINITY_HOME/project/fir
        > efx_run.py fir.xml

    Windows:
        > cd %EFINITY_HOME%\project\fir
        > efx_run.py fir.xml

    The message log will be stored in the outflow/fir.log file.

To view more options, run "efx_run.py --help"
