The settings in this tab apply to all lanes in the same quad.
Table 1. Common Properties Tab: Config Sub-Tab Settings
| Parameter |
Choices |
Notes |
| Common Instance Name |
User defined |
Default: cmn_inst1. This field defines the prefix that is applied to all common
signals. |
| Reference Clock Source |
External |
You must use an external clock. |
| Clock |
CMN_REFCLK0 |
Defaults to CMN_REFCLK0. Block Editor shows the name of the resource that you
should use for this clock. |
| Enable 50 Ω to ground on-die termination for REFCLK0 |
On, off |
Default: on. Indicate whether to use on-die termination for the reference
clock. |
Table 2. Common Properties Tab: APB Sub-Tab
| Parameter |
Selection |
Notes |
| Enable Advanced Peripheral Bus |
On, off |
Default: on. This setting allows you to use the APB to control the PMA Direct
registers. |
| APB Clock Pin Name |
User defined |
Specify the pin name. |
| Invert APB Clock Pin |
On, off |
Default: off. Indicate whether to invert the clock signal. |
| Pin and bus names |
User defined |
Define the APB pin names. Efinix recommends using the default
names. |
Table 3. Common Properties Tab:
Clock and
Reset Sub-Tab Settings
| Parameter |
Selection |
Notes |
| Enable
PHY Quad Reset Pin |
On,
off |
Default:
off. Turn on to specify a reset pin name for the quad. |
| PHY Quad Reset Pin Name |
User defined |
Specify the reset pin name. |
Table 4. Common Properties Tab: Error And Status Sub-Tab Settings
| Parameter |
Selection |
Notes |
| PHY Ready Pin Name |
User defined |
Define the pin name. Efinix recommends using the default
name. |