Design Check: PCI Express Messages (Titanium)

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

pcie_rule_apb_clock (error)

Message PLL <PLL instance name> with output clock driving APB clock must have its reference clock mode set to external
To fix

In the PLL Clock Calculator, set PLL reference clock mode to external for the PLL instance in the message.
Message

PLL <PLL instance name> with output clock driving APB clock must be configured as local feedback mode
To fix In the PLL Clock Calculator, set PLL reference clock mode to local feedback for the PLL instance in the message.
Message APB Clock from PLL frequency is <#> and expected to be <#> MHz
To fix Change the PLL frequency to <#> MHz.
Message APB Clock pin cannot be empty
To fix Enter the APB clock pin name (Block Editor > Pins tab > APB sub-tab > APB Interface Clock Pin Name).

pcie_rule_axi (error)

Message At least either AXI Master or AXI Slave has to be enabled
To fix Enable a master or slave interface (Block Editor > Pins tab > AXI sub-tab).

pcie_rule_axi_clock (error)

Message PCIe AXI Clock from PLL frequency <#>MHx is out of range. Min=<#>MHz Max=<#>MHz
To fix Change the PLL frequency to a valid range. The expected range is 125 to 250 MHz.
Message AXI Clock pin name has not been configured
To fix Enter the AXI clock pin name (Block Editor > Pins tab > AXI sub-tab > AXI Clock Pin Name).

pcie_rule_external_clock (error)

Message PCIE only allows external clock 0 to be configured.
To fix In the <project>.peri.xml file, update the value of PMA_CMN__cmn_plllc_gen_preg__cmn_plllc_pfdclk1_sel_preg to Refclk 0.

pcie_rule_generation (error)

Message PCIe Gen4 is not supported in device <device name>
To fix Topaz FPGAs do not support PCIe Gen 4. Choose another option.

pcie_rule_hw_drc (error)

Message Invalid value assigned to the following parameters: <list_of_parameters>
Found <#> HW Errors: <list_of_errors>
To fix Enter valid values for the parameters.

pcie_rule_hw_drc (warning)

Message
Found <#> HW Warnings: <list_of_warnings>
To fix Enter valid values for the parameters.

pcie_rule_inst_name (error)

Message Instance name is empty.
Valid characters are alphanumeric characters with dash and underscore only
To fix Enter a valid pin name.

pcie_rule_invalid_hex_value (error)

Message The following hexadecimal parameters has invalid value: <list_of_parameters_with_error_message>
To fix Update the parameters to use a hexadecimal value in a valid range.

pcie_rule_osc_clock (error)

Message Oscillator is required to be configured
To fix Create an Oscillator instance with no enable pin.

pcie_rule_perstn (error)

Message PERSTN resource <resource_name> is not configured as perstn connection
To fix Set the connection type for the GPIO instance with resource <resource_name> to pcie_perstn. See GPIO Block (PERST_N).
Message PERSTN resource <resource_name> input name is empty
To fix Enter an input name for the GPIO instance with resource <resource_name>.
Message PERSTN resource <resource_name> is not configured as input
To fix Set the mode to input for GPIO instance with resource <resource_name>.
Message The PERSTN resource <resource_name> has not been configured
To fix Create a GPIO instance with resource <resource_name>.

pcie_rule_pm_clock (error)

Message Empty power management clock pin name
To fix Enter the power management clock pin name or disable power management (Block Editor > Pins tab > Power Management sub-tab).

pcie_rule_refclk (error)

Message Invalid <external_reference_clock> selection due to pins not available in device
To fix Assign external reference clock resource that exists in the FPGA. Check the spelling of the resource name if you are using the Python API.
Message PLL instance with resource <PLL resource list> is required to be configured when reference clock is not from on-board crystal
To fix Create a PLL instance and assign one of the resources listed in the message, or turn on the PCI Express block > Base tab > Reference clock from on-board crystal option.
Message Either one of the following PLL instance(s) required to enable output clock when reference clock is not from on-board crystal: <list of PLL instances with expected output clock>
To fix Enable the output clock for one of the named PLL instances.
Message Either one of the following PLL instance(s) required to use <list of reference clock source> as exteranl reference clock source when PCIe reference clock is not from on-board crystal: <list of PLL instances>
To fix For one of the PLL instances, set external reference clock and use the listed resource as the reference clock source.
Message Either one of the following PLL instance(s) required to use local feedback mode when reference clock is not from on-board crystal: <list of PLL instances>
To fix Change the PLL's feedback mode to local for one of the named PLL instances.
Message Core refclk pin has to be specified in core mode
To fix Enter a reference clock pin name (Qn_REFCLK0/1_N/P). Check the spelling of the resource name if you are using the Python API.
Message Reference clock PLL resource <PLL_resource_name> Output Clock <#> has not been configured
To fix Create a PLL instance with resource <PLL_resource_name> and enable output clock <#>.
Message Reference clock PLL resource <PLL_resource_name> has not been configured
To fix Create PLL instance with resource <PLL_resource_name>.
Message Invalid reference clock since PLL does not exists in the device
To fix Choose another connection type.

pcie_rule_resource (error)

Message Resource name is empty
To fix Assign a resource.
Message Resource is not a valid PCIe device instance
To fix Assign the instance to a resource that exists in the FPGA. Check the spelling of the resource name if you are using the Python API.