Reference Clock Selection
You
can change the PLL's reference
clock
by controlling the reference clock selection port,
REFCLK_SEL.
When the PLL Dynamic Reconfiguration is
enabled, the
core
drives the
REFCLK_SEL
port
as illustrated in Figure 1.
Note: The
REFCLK_SEL
port
is only active after the powers
up, i.e., after
the
FPGA enters user mode. Hence, it is essential that the initial value
of this REFCLK_SEL
port
matches the
bitstream's
original PCR settings to prevent unintentional reference clock input
switching.