PLL Dynamic Reconfiguration Core User Guide

The PLL Dynamic Reconfiguration core allows users to change the PLL settings on an Efinix FPGA, without changing the settings in the Interface Designer, re-compiling, and re-generating the bitstream file. This IP core provides an efficient way to change the PLL settings on the fly after initial boot-up, without having to re-configure the FPGA.

Use the IP Manager to select IP, customize it, and generate files. The PLL Dynamic Reconfiguration core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.

This help gives you an overview of the PLL Dynamic Reconfiguration core and how to configure it with the IP Manager. For detailed information, refer to PLL Dynamic Reconfiguration Core User Guide in the Support Center.

Features

The PLL Dynamic Reconfiguration core includes the following features:

  • Allows up to 85 PLL settings to be stored and reconfigure the PLL
  • Allows the FPGA to revert to the original PLL settings in the bitstream file1
  • Single configuration and multiple configuration mode

Functional Description

The PLL Dynamic Reconfiguration core is positioned between the user's logic and the PLL to facilitate the dynamic reconfiguration scheme.

Figure 1. PLL Dynamic Reconfiguration Block Diagram

Interface Designer Settings

Before generating the PLL Dynamic Reconfiguration core in the Efinity IP Manager, you must set up a PLL Block and generate a RAM Hex File in the Interface Designer. The RAM Hex File contains one or more PLL configuration settings to be stored in the built-in RAM in the PLL Dynamic Reconfiguration core.

Set Up the PLL and Enable the Dynamic Reconfiguration

For more information on setting up the PLL, refer to PLL Interface in the interfaces user guide. To enable the PLL Dynamic Reconfiguration core, follow these steps:
  1. In the Interface Designer, add a PLL block.
  2. Click Automated Clock Calculation to open the PLL Clock Calulator.
  3. Specify a reference clock frequency.
  4. Turn on the Reset Pin option and enter the name user_pll_en.
  5. Turn on the Locked Pin option and enter the name pll_lock.
  6. Click Finish to close the PLL Clock Calculator.
  7. Click the Advanced Settings tab.
  8. Turn on Enable under Dynamic Reconfiguration.
  9. Enter the reference clock names.
  10. Create GPIO blocks for any external clocks and core clocks as needed. All clock names should be the same as the ones that you are using in your design. Names are case sensitive.

Generate the RAM Hex File

To generate a RAM Hex File, follow these steps in the Interface Designer for the PLL block you just created:
  1. Click Advanced Settings > Reconfiguration Wizard to open the PLL Dynamic Reconfiguration Wizard.
  2. Click Add. In the Record Name box, a new configuration setting names would appear, along with the numbering on the left column.
    Note: The numbering on the left column is the ID of the configuration settings. During the Dynamic Reconfiguration with Multiple Configuration, you need to drive the signal mif_selection based on this ID.
  3. Click on the configuration file that you have just added and start customizing the configuration settings.
  4. Once you finish customizing the configuration settings, click Verify.
  5. Repeat steps 2, 3, and 4 to add as many configurations (up to 85 configurations) as desired.
  6. Enter a filename in the PLL Dynamic Reconfiguration File box or use the default filename.
  7. Finally, click Export.

Figure 2. PLL Dynamic Reconfiguration Wizard

IP Manager

The Efinity® IP Manager is an interactive wizard that helps you customize and generate Efinix® IP cores. The IP Manager performs validation checks on the parameters you set to ensure that your selections are valid. When you generate the IP core, you can optionally generate an example design targeting an Efinix development board and/or a testbench. This wizard is helpful in situations in which you use several IP cores, multiple instances of an IP core with different parameters, or the same IP core for different projects.

Note: Not all Efinix IP cores include an example design or a testbench.

The IP Manager is included with the Efinity software v2020.2 and higher.

The IP Manager consists of:
  • IP Catalog—Provides a catalog of IP cores you can select. Open the IP Catalog using the toolbar button or using Tools > Open IP Catalog.
  • IP Configuration—Wizard to customize IP core parameters, select IP core deliverables, review the IP core settings, and generate the custom variation.
  • IP Editor—Helps you manage IP, add IP, and import IP into your project.

Generating the PLL Dynamic Reconfiguration Core with the IP Manager

The following steps explain how to customize an IP core with the IP Configuration wizard.
  1. Open the IP Catalog.
  2. Choose Foundation IP > PLL Dynamic Reconfiguration core and click Next. The IP Configuration wizard opens.
  3. Enter the module name in the Module Name box.
    Note: You cannot generate the core without a module name.
  4. Customize the IP core using the options shown in the wizard. For detailed information on the options, refer to the Customizing the PLL Dynamic Reconfiguration Core section.
  5. In the Initial Reference Clock Setting, key in the reference clock setting.
    Note: This reference clock setting must match the clock source of the PCR setting to prevent unintended clock switching during the FPGA power up. Refer to Reference Clock Selection.
  6. (Optional) In the Deliverables tab, specify whether to generate an IP core example design targeting an Efinix® development board and/or testbench. These options are turned on by default.
  7. (Optional) In the Summary tab, review your selections.
  8. Click Generate to generate the IP core and other selected deliverables.
  9. In the Review configuration generation dialog box, click Generate. The Console in the Summary tab shows the generation status.
    Note:
    • The PLL instance name is the same name you have created for the targeted PLL in Interface Designer.
    • Ensure that the Initial Reference Clock Setting is the same with what you have selected in the interface designer.
    • You can disable the Review configuration generation dialog box by turning off the Show Confirmation Box option in the wizard.
  10. When generation finishes, the wizard displays the Generation Success dialog box. Click OK to close the wizard.

The wizard adds the IP to your project and displays it under IP in the Project pane.

Generated Files

The IP Manager generates these files and directories:
  • <module name>_define.svh—Contains the customized parameters.
  • <module name>_tmpl.sv—Verilog HDL instantiation template.
  • <module name>_tmpl.vhd—VHDL instantiation template.
  • <module name>.sv—IP source code.
  • settings.json—Configuration file.
  • <kit name>_devkit—Has generated RTL, example design, and Efinity® project targeting a specific development board.
  • Testbench—Contains generated RTL and testbench files.

Instantiating the IP

The IP Manager creates these template files in the <project>/ip/<module name> directory:
  • <module name>.v_tmpl.sv is the Verilog HDL module.
  • <module name>.v_tmpl.vhd is the VHDL component declaration and instantiation template.
To use the IP, copy and paste the code from the template file into your design and update the signal names to instantiate the IP.
Important: When you generate the IP, the software automatically adds the module file (<module name>.v) to your project and lists it in the IP folder in the Project pane. Do not add the <module name>.v file manually (for example, by adding it using the Project Editor); otherwise the Efinity® software will issue errors during compilation.

Customizing the PLL Dynamic Reconfiguration Core

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. PLL Dynamic Reconfiguration Core Parameter
Parameter Options Description
Configuration Mode Multi Configuration, Single Configuration Multi Configuration: Select multi-configuration if you want to use more than one PLL configuration setting.
Single Configuration: Select single configuration to optimize the resources if you are only uisng one configuration.
RAM Hex File Path – For multiple configuration, browse to the RAM Hex file path. Refer to Generate the RAM Hex File topic to create a RAM Hex file if it is unavailable.
To generate the IP successfully, make sure you select the correct file.
Configuration Setting – For single configuration, you need to enter the configuration setting (which is a string) into this box. To obtain the configuration setting string, open the <generated RAM Hex file>.dyn_cfg.rpt file.
This report file is generated when the <generated RAM Hex file>.hex is generated.
PLL Instance Name – Enter the PLL block name you created in the Interface Designer for the PLL you want to reconfigure.
Reference Clock Setting External Clock 0,
External Clock 1,
Core Clock 0,
Core Clock 1		 Initial reference clock.
Default: External clock 0
This option is the same as the Interface Designer's reference clock settings.
1 The original PLL settings are also known as Peripheral Configuration Register (PCR) settings.