Ethernet 10G MAC Core User Guide

The Ethernet 10G MAC core is a configurable core that supports Ethernet speeds up to 10 Gbps in full duplex transfer mode. The core complies with the IEEE Std. 802.3-2008 specification and operates at a frequency of 156.25 MHz.

Additionally, the Ethernet 10G MAC core is designed to interact with the user’s logic and the FPGA Ethernet 10G physical coding sublayer (PCS) as shown in Figure 1. The interaction between the user’s logic, Ethernet 10G MAC core, and the FPGA PCS are based on a per-lane basis.

Figure 1. Ethernet 10G MAC Core Interaction with User’s Logic and the FPGA Ethernet 10G PCS

At the FPGA transceiver’s end, the APB interface is per quad basis, which is a common interface shared across 4 lanes in the FPGA Ethernet 10G PCS. For more information, see Titanium Ethernet 10GBase-KR User Guide.

Use the IP Manager to select IP, customize it, and generate files. The Ethernet 10G MAC core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.

This help gives you an overview of the Ethernet 10G MAC core and how to configure it with the IP Manager. For detailed information, refer to Ethernet 10G MAC User Guide in the Support Center.

Features

  • Complies with IEEE Std. 802.3-2008 specification
  • Supports 10 Gbps Ethernet in full duplex transfer mode
  • Single clock operates at 156.25 MHz
  • AXI4 ST 64-bit user interface at transmit and receiver interfaces
  • Configurable Cut Through mode to transfer the Ethernet frame with minimum latency
  • Configurable Store Forward mode where the entire Ethernet frame is received first before the transfer begins
  • Programmable inter packet gap (IPG)
  • Automatic padding for short frames
  • Frame check sequence and CRC generation, includes checking and forwarding
  • Automatic termination of bad frames
  • Frame length check based on user-defined MTU frame length
  • Automatic frame length check against ETHERTYPE/LEN field for frames
  • Broadcast, Unicast, and multicast address filtering
  • Flow control through pause frame generation and decoding
  • Statistics reporting

Functional Description

The Ethernet 10G MAC core does the following functions:
  • Converts TX data packets from AXI ST to XGMII format.
  • Decodes RX Data Packets from XGMII format to AXI ST.
  • Generates the pause frame to be transmitted at the XGMII Interface.
  • Identifies the pause frame and implements the flow control through the pause mechanism based on the decoded PAUSE_QUANT.
  • Drops RX Frames with mismatched address through a bit-wise address filtering mask.
  • Drops RX Frames with broadcast address.

IP Manager

The Efinity® IP Manager is an interactive wizard that helps you customize and generate Efinix® IP cores. The IP Manager performs validation checks on the parameters you set to ensure that your selections are valid. When you generate the IP core, you can optionally generate an example design targeting an Efinix development board and/or a testbench. This wizard is helpful in situations in which you use several IP cores, multiple instances of an IP core with different parameters, or the same IP core for different projects.

Note: Not all Efinix IP cores include an example design or a testbench.

The IP Manager is included with the Efinity software v2020.2 and higher.

The IP Manager consists of:
  • IP Catalog—Provides a catalog of IP cores you can select. Open the IP Catalog using the toolbar button or using Tools > Open IP Catalog.
  • IP Configuration—Wizard to customize IP core parameters, select IP core deliverables, review the IP core settings, and generate the custom variation.
  • IP Editor—Helps you manage IP, add IP, and import IP into your project.

Generating the Ethernet 10G MAC Core with the IP Manager

The following steps explain how to customize an IP core with the IP Configuration wizard.
  1. Open the IP Catalog.
  2. Choose Ethernet > 10G Ethernet MAC core and click Next. The IP Configuration wizard opens.
  3. Enter the module name in the Module Name box.
    Note: You cannot generate the core without a module name.
  4. Customize the IP core using the options shown in the wizard. For detailed information on the options, refer to the Customizing the Ethernet 10G MAC section.
  5. (Optional) In the Deliverables tab, specify whether to generate an IP core example design targeting an Efinix® development board and/or testbench. These options are turned on by default.
  6. (Optional) In the Summary tab, review your selections.
  7. Click Generate to generate the IP core and other selected deliverables.
  8. In the Review configuration generation dialog box, click Generate. The Console in the Summary tab shows the generation status.
    Note: You can disable the Review configuration generation dialog box by turning off the Show Confirmation Box option in the wizard.
  9. When generation finishes, the wizard displays the Generation Success dialog box. Click OK to close the wizard.

The wizard adds the IP to your project and displays it under IP in the Project pane.

Generated Files

The IP Manager generates these files and directories:
  • <module name>_define.svh—Contains the customized parameters.
  • <module name>_tmpl.sv—Verilog HDL instantiation template.
  • <module name>_tmpl.vhd—VHDL instantiation template.
  • <module name>.sv—IP source code.
  • settings.json—Configuration file.
  • efx_ethernet_10g_exp—Has generated RTL, example design, and Efinity® project targeting a specific development board.
  • Testbench—Contains simulation models. Testbench is not available.

Instantiating the IP

The IP Manager creates these template files in the <project>/ip/<module name> directory:
  • <module name>_tmpl.sv is the System Verilog HDL module.
  • <module name>_tmpl.vhd is the VHDL component declaration and instantiation template.
To use the IP, copy and paste the code from the template file into your design and update the signal names to instantiate the IP.
Important: When you generate the IP, the software automatically adds the module file (<module name>.v) to your project and lists it in the IP folder in the Project pane. Do not add the <module name>.v file manually (for example, by adding it using the Project Editor); otherwise the Efinity® software will issue errors during compilation.

Efinity: IP Catalog, Interface Designer, and Integration

The Ethernet 10G MAC core is designed to interact with the user's logic and the FPGA Ethernet 10G PCS as shown in Figure 1. To combine the Ethernet 10G MAC core, the FPGA Ethernet 10G PCS and user's logic together as a whole design, you need to perform the following steps:
  1. Configure and generate the Ethernet 10G MAC core from the IP Catalog.
  2. Configure and generate the FPGA Ethernet 10G PCS using the Interface Designer.
  3. Create a top-level module to integrate the Ethernet 10G MAC core (from step 1), the FPGA Ethernet 10G PCS (from step 2) and user's logic.

Top Level Module

You need to create a top-level module to integrate the Ethernet 10G MAC core (generated from the IP Catalog) and the FPGA 10G PCS (generated from the Interface Designer).

Figure 2 illustrates the integration of one lane of Ethernet 10G MAC and PCS for Efinity compilation.

Figure 2. Top-Level Module for Efinity Compilation

Customizing the Ethernet 10G MAC

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. Ethernet 10G MAC Core Parameters
Name Options Description
Data Streaming Mode 0, 1 1 = Cut Through (default)
0 = Store Forward
In Cut Through mode, the XGMII packet is transferred with minimum latency, without waiting for the complete packet.
In Store Forward mode, the XGMII packet is only transferred when the entire packet is fully stored.
Programmable Inter packet Gap 9 - 15
Default = 12
In Store Forward mode, the effective IPG may be governed by the Store Forward mechanism, where the packet is only transferred when the entire packet is fully stored.
Maximum Transmission Unit Frame Length 64 - 16018 Default = 1518
Maximum Transmission Unit Frame Length is the total count of headers (destination address, source address, VLAN tag, type/length), data payload and frame check sequence.
Refer to frame length in the Ethernet 10G MAC User Guide.
Any RX packet with physical length > Maximum Transmission Unit Frame Length will be flagged as oversized frame. Any RX packet with payload < 46 will also with undersized frame.
MAC Source Address – Default = 48'h0000_0000_0000
This MAC Source Address is used in the following scenarios:
  • When generating TX pause frame.
  • When comparing against address filtering.
This MAC Source Address is not used when converting from User TX AXI ST inputs to XGMII TX packets.
Broadcast Filtering 0, 1 1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
TXFIFO Depth 8 – 2048 Default: 512
Set the depth of FIFO for storing the Full TX packet during Store Forward mode.
The depth of FIFO must be large enough to store the maximum length of the TX frames intended for transfer.
Refer to "Store Forward Mode" in the Ethernet 10G MAC User Guide
This parameter is not effective during Cut Through mode.
Link Fault Detection 0, 1
1 = Enable Link Fault Detection (Default)
0 = Disable Link Fault Detection