APB Interconnect Core User Guide

The APB Interconnect core provides solution to connect multiple APB masters to a single APB slave. The APB Interconnect core supports two arbitration modes to determine the grant access of the masters. The APB Interconnect core operates based on the AMBA 3 APB protocol specifications version 1.0.

Use the IP Manager to select IP, customize it, and generate files. The APB Interconnect core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.

This help gives you an overview of the APB Interconnect core and how to configure it with the IP Manager. For detailed information, refer to APB Interconnect Core User Guide in the Support Center.

Features

The APB Interconnect core includes the following features:

Compliant with AMBA 3 APB Protocol specifications
Data width up to 32 bits [1, 2, …, 32]
Address width up to 32 bits [1, 2, …, 32]
Fixed-priority and round-robin arbitration modes
Supports arbitration between/up to 32 masters to single slave
Optional pipeline registers to optimize latency or/and performance
Include indicators of request status on which the master is being granted the request

Functional Description

The APB Interconnect core is a bridge to arbitrate among multiple masters to a single slave based on priority level. The APB Interconnect core grants request to master with the selected priority. The APB Interconnect core thas two main interfaces:

APB Master Interface—Provides 32 master interfaces to the core.
APB Slave Interface—Supports single slave interface.

The APB Interconnect core operates based on AMBA 3 APB protocol specifications. The following describes the general operation of the APB Interconnect core:

When apb_eval is asserted, it indicates that APB Interconnect is in evaluation state, where it analyzes all masters' request and decide which master to grant.
During evaluation state (i.e., apb_eval = 1), any assertionof PSEL marks the start of the APB request.
- If it is a APB write request, PWRITE needs to assert too. PADDR and PWDATA contain destination address and the intended DATA to be written.
- If it is a APB read request, PWRITE deasserts PADDR and contain the address of the register to be read.
The PENABLE signal needs to be asserted 1 clock cycle after the assertion of PSEL for the APB request to be successful. The PENABLE assertion marks the start of transfer of the APB request.
The PREADY signal is a return or response signal from the slave. The assertion PREADY indicates that the slave has completed the APB request.
The PRDATA signal contains the result of the APB read request and it is valid when PREADY is 1.
Masters' input signals (PSEL, PENABLE, PWRITE, PADDR, and PWDATA) need to be maintained throughout the APB request, i.e., from the assertion of PSEL until the assertion of PREADY.
Upon receiving PREADY, master may change the PSEL, PENABLE, PWRITE, PADDR, and PWDATA signals for the next request or transfer.

Figure 1. APB Interconnect Core Block Diagram

IP Manager

The Efinity® IP Manager is an interactive wizard that helps you customize and generate Efinix® IP cores. The IP Manager performs validation checks on the parameters you set to ensure that your selections are valid. When you generate the IP core, you can optionally generate an example design targeting an Efinix development board and/or a testbench. This wizard is helpful in situations in which you use several IP cores, multiple instances of an IP core with different parameters, or the same IP core for different projects.

Note: Not all Efinix IP cores include an example design or a testbench.

The IP Manager is included with the Efinity software v2020.2 and higher.

The IP Manager consists of:

IP Catalog—Provides a catalog of IP cores you can select. Open the IP Catalog using the toolbar button or using Tools > Open IP Catalog.
IP Configuration—Wizard to customize IP core parameters, select IP core deliverables, review the IP core settings, and generate the custom variation.
IP Editor—Helps you manage IP, add IP, and import IP into your project.

Generating the APB Interconnect Core with the IP Manager

The following steps explain how to customize an IP core with the IP Configuration wizard.

Open the IP Catalog.
Choose Bridge and Adaptors > APB Interconnect core and click Next. The IP Configuration wizard opens.
Enter the module name in the Module Name box.
Note: You cannot generate the core without a module name.
Customize the IP core using the options shown in the wizard. For detailed information on the options, refer to the Customizing the APB Interconnect section.
(Optional) In the Deliverables tab, specify whether to generate an IP core example design targeting an Efinix® development board and/or testbench. These options are turned on by default.
(Optional) In the Summary tab, review your selections.
Click Generate to generate the IP core and other selected deliverables.
In the Review configuration generation dialog box, click Generate. The Console in the Summary tab shows the generation status.
Note: You can disable the Review configuration generation dialog box by turning off the Show Confirmation Box option in the wizard.
When generation finishes, the wizard displays the Generation Success dialog box. Click OK to close the wizard.

The wizard adds the IP to your project and displays it under IP in the Project pane.

Generated Files

The IP Manager generates these files and directories:

<module name>_define.svh—Contains the customized parameters.
<module name>_tmpl.sv—Verilog HDL instantiation template.
<module name>_tmpl.vhd—VHDL instantiation template.
<module name>.sv—IP source code.
settings.json—Configuration file.
Testbench—Contains generated RTL and testbench files.

Instantiating the IP

The IP Manager creates these template files in the <project>/ip/<module name> directory:

<module name>.v_tmpl.v is the Verilog HDL module.
<module name>.v_tmpl.vhd is the VHDL component declaration and instantiation template.

To use the IP, copy and paste the code from the template file into your design and update the signal names to instantiate the IP.

Important: When you generate the IP, the software automatically adds the module file (<module name>.v) to your project and lists it in the IP folder in the Project pane. Do not add the <module name>.v file manually (for example, by adding it using the Project Editor); otherwise the Efinity® software will issue errors during compilation.

Customizing the APB Interconnect

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. APB Interconnect Core Parameters (General Tab)
Port	Options	Description
Master Arbitration Mode	Fixed Priority, Round Robin	Defines the arbitration mode on master interface. Default: Fixed Priority
Number of Master	2 - 32	Defines the number of masters to be enabled. Default: 32
Data Width	1 - 32	Defines the data width of each Master. The N-to-1 relationship of the number of masters and slaves where the slave is the common destination for all the masters. Hence, the data width of each master should match the data width of the slave. Default: 32
Address Width	1 - 32	Defines the address width of each master. The N-to-1 relationship of the number of masters and slaves where the slave is the common destination for all the masters. Hence, the address width of each master should match the address width of the slave. Default: 32
Optional APB Signals	On, Off	Defines the additional APB Signals for non-APB3. The signals are applicable when the data width is in multiple of 8-bit. Select On to enable Optional APB Signals, The Optional APB Signals are as follows: APB_PRDATA_PAR APB_PWDATA_PAR APB_PSTRB_PAR APB_PSTRB Default: Off
Register Input	On, Off	Defines register on the master input signals. Select On to enable Pipeline Registers at the master interface input paths that includes s_apb_psel_i, s_apb_penable_i, s_apb_pwrite_i, s_apb_paddr_i, s_apb_pwdata_i, s_apb_pwdata_par_i, s_apb_pstrb_i and s_apb_pstrb_par_i. Default: On
Register Output	On, Off	Defines register on the output-to-master signals. Select On to enable Pipeline Registers at the master interface output paths, namely s_apb_pready_o, s_apb_pslverr_o, s_apb_prdata_o and s_apb_prdata_par_o. Default: On
Optimize Latency	On, Off	Defines register on the output-to-slave signals. Select On to optimize latency by disabling Pipeline Registers at the slave interface, namely apb_sel_o, apb_penable_o, apb_pwrite_o, apb_paddr_o, apb_pwdata_o, apb_pwdata_par_o, apb_pstrb_o and apb_pstrb_par_o. Default: Off
Master n Priority	Where number of master, n = 0, 1, 2, …, 31	Defines the priority of each master in descending order, i.e., master with priority `1` has the highest priority, while a master with priority `32` has the lowest priority. This setting is only applicable when the Master Arbitration mode = Fixed Priority. This parameter depends on the number of master. For example, if the number of master = 3, the following 3 parameters appear: Master 0 Priority Master 1 Priority Master 2 Priority Default Setting: Each Master is assigned with priority in descending order, e.g., Master 0 Priority = 1 (Highest Priority) Master 1 Priority = 2 Master 2 Priority =3 (Lowest Priority)